[llvm] r323263 - [X86] Merge some regular expressions in Zen scheduler model and remove 2 unused classes.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Tue Jan 23 13:37:56 2018
New Revision: 323263

URL: http://llvm.org/viewvc/llvm-project?rev=323263&view=rev
Log:
[X86] Merge some regular expressions in Zen scheduler model and remove 2 unused classes.

I don't know if the unused classes were intended to be used and that the VEX version is really different than the legacy SSE version. Agner's tables don't show any differences. I'm just cleaning up assuming the current behavior is correct.

Modified:
    llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td

Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=323263&r1=323262&r2=323263&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Tue Jan 23 13:37:56 2018
@@ -1431,23 +1431,11 @@ def ZnWriteCVSTSI2SILd: SchedWriteRes<[Z
 }
 // CVTSD2SI.
 // r32/64
-def : InstRW<[ZnWriteCVSTSI2SIr], (instregex "CVT(T?)SD2SI(64)?rr")>;
+def : InstRW<[ZnWriteCVSTSI2SIr], (instregex "(V?)CVT(T?)SD2SI(64)?rr")>;
 // r32,m32.
-def : InstRW<[ZnWriteCVSTSI2SILd], (instregex "CVT(T?)SD2SI(64)?rm")>;
+def : InstRW<[ZnWriteCVSTSI2SILd], (instregex "(V?)CVT(T?)SD2SI(64)?rm")>;
 
 
-def ZnWriteVCVSTSI2SIr: SchedWriteRes<[ZnFPU3]> {
-  let Latency = 5;
-}
-def ZnWriteVCVSTSI2SILd: SchedWriteRes<[ZnFPU3, ZnAGU]> {
-  let Latency = 12;
-}
-// VCVTSD2SI.
-// r32/64
-def : InstRW<[ZnWriteCVSTSI2SIr], (instregex "VCVT(T?)SD2SI(64)?rr")>;
-// r32,m32.
-def : InstRW<[ZnWriteCVSTSI2SILd], (instregex "VCVT(T?)SD2SI(64)?rm")>;
-
 // VCVTPS2PH.
 // x,v,i.
 def : InstRW<[WriteMicrocoded], (instregex "VCVTPS2PH(Y?)rr")>;