[llvm] r323258 - Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Tue Jan 23 13:22:16 2018
New Revision: 323258

URL: http://llvm.org/viewvc/llvm-project?rev=323258&view=rev
Log:
Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=323258&r1=323257&r2=323258&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Tue Jan 23 13:22:16 2018
@@ -3038,7 +3038,7 @@ HexagonTargetLowering::LowerBUILD_VECTOR
     // Always produce 8 bits, repeat inputs if necessary.
     unsigned Rep = 8 / VecTy.getVectorNumElements();
     for (unsigned i = 0; i != 8; ++i) {
-      SDValue S = DAG.getConstant(1 << i, dl, MVT::i32);
+      SDValue S = DAG.getConstant(1ull << i, dl, MVT::i32);
       Rs[i] = DAG.getSelect(dl, MVT::i32, Ops[i/Rep], S, Z);
     }
     for (ArrayRef<SDValue> A(Rs); A.size() != 1; A = A.drop_back(A.size()/2)) {