[llvm] r323205 - AArch64: get type from correct result when forming BFX

[Tim Northover via llvm-commits]

Author: tnorthover
Date: Tue Jan 23 07:11:27 2018
New Revision: 323205

URL: http://llvm.org/viewvc/llvm-project?rev=323205&view=rev
Log:
AArch64: get type from correct result when forming BFX

Some nodes produce multiple values so when obtaining the type of an ISD::OR we
need to make sure we ask for the correct one. Hopefully that's all of them.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    llvm/trunk/test/CodeGen/AArch64/bitfield-extract.ll

Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp?rev=323205&r1=323204&r2=323205&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp Tue Jan 23 07:11:27 2018
@@ -1681,7 +1681,7 @@ static bool isBitfieldExtractOpFromShr(S
     // later find more redundancy.
     Opd0 = N->getOperand(0).getOperand(0);
     TruncBits = Opd0->getValueType(0).getSizeInBits() - VT.getSizeInBits();
-    VT = Opd0->getValueType(0);
+    VT = Opd0.getValueType();
     assert(VT == MVT::i64 && "the promoted type should be i64");
   } else if (BiggerPattern) {
     // Let's pretend a 0 shift left has been performed.

Modified: llvm/trunk/test/CodeGen/AArch64/bitfield-extract.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/bitfield-extract.ll?rev=323205&r1=323204&r2=323205&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/bitfield-extract.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/bitfield-extract.ll Tue Jan 23 07:11:27 2018
@@ -96,3 +96,20 @@ define void @test11(i64 %a) {
 }
 
 declare void @use(i16 signext, i64)
+
+; CHECK-LABEL: test_complex_node:
+; CHECK: ldr d0, [x0], #8
+; CHECK: ubfx x[[VAL:[0-9]+]], x0, #5, #27
+; CHECK: str w[[VAL]], [x2]
+define <2 x i32> @test_complex_node(<2 x i32>* %addr, <2 x i32>** %addr2, i32* %bf ) {
+  %vec = load <2 x i32>, <2 x i32>* %addr
+
+  %vec.next = getelementptr <2 x i32>, <2 x i32>* %addr, i32 1
+  store <2 x i32>* %vec.next, <2 x i32>** %addr2
+  %lo = ptrtoint <2 x i32>* %vec.next to i32
+
+  %val = lshr i32 %lo, 5
+  store i32 %val, i32* %bf
+
+  ret <2 x i32> %vec
+}