[llvm] r323173 - [X86] Various vXi1 insertion improvements.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 22 21:36:53 PST 2018
Author: ctopper
Date: Mon Jan 22 21:36:53 2018
New Revision: 323173
URL: http://llvm.org/viewvc/llvm-project?rev=323173&view=rev
Log:
[X86] Various vXi1 insertion improvements.
Add missing patterns for inserting v1i1 into a zero vector. Use insert_subvector to zero upper bits before inserting an element into a vXi1 vector. Replace kshift based isel pattern with insert_subvector based pattern now that code that caused the pattern has been fixed to emit insert_subvector.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/lib/Target/X86/X86InstrVecCompiler.td
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=323173&r1=323172&r2=323173&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jan 22 21:36:53 2018
@@ -14920,12 +14920,12 @@ static SDValue InsertBitToMaskVector(SDV
}
// Insertion of one bit into first position
- if (IdxVal == 0 ) {
+ if (IdxVal == 0) {
// Clean top bits of vector.
- EltInVec = DAG.getNode(X86ISD::KSHIFTL, dl, VecVT, EltInVec,
- DAG.getConstant(NumElems - 1, dl, MVT::i8));
- EltInVec = DAG.getNode(X86ISD::KSHIFTR, dl, VecVT, EltInVec,
- DAG.getConstant(NumElems - 1, dl, MVT::i8));
+ EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i1, Elt);
+ EltInVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VecVT,
+ getZeroVector(VecVT, Subtarget, DAG, dl),
+ EltInVec, DAG.getIntPtrConstant(0, dl));
// Clean the first bit in source vector.
Vec = DAG.getNode(X86ISD::KSHIFTR, dl, VecVT, Vec,
DAG.getConstant(1 , dl, MVT::i8));
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=323173&r1=323172&r2=323173&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Mon Jan 22 21:36:53 2018
@@ -2761,19 +2761,12 @@ let Predicates = [HasAVX512] in {
defm : operation_gpr_mask_copy_lowering<VK32, v32i1>;
defm : operation_gpr_mask_copy_lowering<VK64, v64i1>;
- def : Pat<(X86kshiftr (X86kshiftl (v1i1 (scalar_to_vector GR8:$src)), (i8 15)), (i8 15)) ,
- (COPY_TO_REGCLASS
- (KMOVWkr (AND32ri8 (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
- GR8:$src, sub_8bit), (i32 1))), VK1)>;
- def : Pat<(X86kshiftr (X86kshiftl (v16i1 (scalar_to_vector GR8:$src)), (i8 15)), (i8 15)) ,
+ def : Pat<(insert_subvector (v16i1 immAllZerosV),
+ (v1i1 (scalar_to_vector GR8:$src)), (iPTR 0)),
(COPY_TO_REGCLASS
- (KMOVWkr (AND32ri8 (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
- GR8:$src, sub_8bit), (i32 1))), VK16)>;
- def : Pat<(X86kshiftr (X86kshiftl (v8i1 (scalar_to_vector GR8:$src)), (i8 15)), (i8 15)) ,
- (COPY_TO_REGCLASS
- (KMOVWkr (AND32ri8 (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
- GR8:$src, sub_8bit), (i32 1))), VK8)>;
-
+ (KMOVWkr (AND32ri8
+ (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src, sub_8bit),
+ (i32 1))), VK16)>;
}
// Mask unary operation
Modified: llvm/trunk/lib/Target/X86/X86InstrVecCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrVecCompiler.td?rev=323173&r1=323172&r2=323173&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrVecCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrVecCompiler.td Mon Jan 22 21:36:53 2018
@@ -497,6 +497,11 @@ let Predicates = [HasBWI, HasVLX] in {
// using shifts.
let Predicates = [HasAVX512] in {
def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
+ (v1i1 VK1:$mask), (iPTR 0))),
+ (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK1:$mask, VK16),
+ (i8 15)), (i8 15))>;
+
+ def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
(v2i1 VK2:$mask), (iPTR 0))),
(KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK2:$mask, VK16),
(i8 14)), (i8 14))>;
@@ -520,6 +525,10 @@ let Predicates = [HasDQI] in {
(COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK16)>;
def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
+ (v1i1 VK1:$mask), (iPTR 0))),
+ (KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK1:$mask, VK8),
+ (i8 7)), (i8 7))>;
+ def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
(v2i1 VK2:$mask), (iPTR 0))),
(KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK2:$mask, VK8),
(i8 6)), (i8 6))>;
@@ -566,6 +575,10 @@ let Predicates = [HasBWI, HasDQI] in {
let Predicates = [HasBWI, HasVLX] in {
def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
+ (v1i1 VK1:$mask), (iPTR 0))),
+ (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK1:$mask, VK32),
+ (i8 31)), (i8 31))>;
+ def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
(v2i1 VK2:$mask), (iPTR 0))),
(KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK2:$mask, VK32),
(i8 30)), (i8 30))>;
@@ -575,6 +588,10 @@ let Predicates = [HasBWI, HasVLX] in {
(i8 28)), (i8 28))>;
def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
+ (v1i1 VK1:$mask), (iPTR 0))),
+ (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK1:$mask, VK64),
+ (i8 63)), (i8 63))>;
+ def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
(v2i1 VK2:$mask), (iPTR 0))),
(KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK2:$mask, VK64),
(i8 62)), (i8 62))>;
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