[PATCH] D29935: [RISCV 13/n] Codegen for conditional branches

[Alex Bradbury via Phabricator via llvm-commits]

asb added a subscriber: kparzysz.
asb added inline comments.


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Comment at: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td:70
 // A 13-bit signed immediate where the least significant bit is zero.
-def simm13_lsb0 : Operand<XLenVT> {
+def simm13_lsb0 : Operand<OtherVT> {
   let ParserMatchClass = SImmAsmOperand<13, "Lsb0">;
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sabuasal wrote:
> Hi Alex, 
> 
> I have two questions about this:
> 1)  Why don't we have this type inherting from ImmLeaf?
> 2) Why is this not using XLenVT?
> 
> I am trying to add ImmLeaf since I need them for some checks for that type but it is causing a crash while running table gen about some type compatibility ("Type set is empty for each HW mode")
As you've noted, it doesn't work when defined as an immediate type. I noted this in the patch description for this review, but nobody seems to have had any ideas on retaining `def simm21_lsb0 : Operand<XLenVT>`. Ultimately, branch operands are always symbols during codegen rather than immediates. Every other backend I checked ended up using `Operand<OtherVT>` for branch targets which at least implies I'm not missing something obvious. I think ideally we'd be able to specify that symbol operands are coerced to XLenVT.

If there's no cleaner solution, I suppose you could define a `simm13_lsb0pred`  and use that in pattern definitions for instruction compression transformations. I don't like that we lose consistency with other operand definitions of course...

@kparzysz may be able to give more insight into the TableGen type check error.


Repository:
  rL LLVM

https://reviews.llvm.org/D29935