[llvm] r323074 - [NFC] fix trivial typos in comments
Hiroshi Inoue via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 21 21:54:46 PST 2018
Author: inouehrs
Date: Sun Jan 21 21:54:46 2018
New Revision: 323074
URL: http://llvm.org/viewvc/llvm-project?rev=323074&view=rev
Log:
[NFC] fix trivial typos in comments
"the the" -> "the"
Modified:
llvm/trunk/lib/Target/AMDGPU/GCNSchedStrategy.cpp
llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h
llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp
llvm/trunk/lib/Target/Lanai/LanaiInstrFormats.td
llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/GCNSchedStrategy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/GCNSchedStrategy.cpp?rev=323074&r1=323073&r2=323074&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/GCNSchedStrategy.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/GCNSchedStrategy.cpp Sun Jan 21 21:54:46 2018
@@ -81,7 +81,7 @@ void GCNMaxOccupancySchedStrategy::initC
Cand.AtTop = AtTop;
// getDownwardPressure() and getUpwardPressure() make temporary changes to
- // the the tracker, so we need to pass those function a non-const copy.
+ // the tracker, so we need to pass those function a non-const copy.
RegPressureTracker &TempTracker = const_cast<RegPressureTracker&>(RPTracker);
std::vector<unsigned> Pressure;
Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=323074&r1=323073&r2=323074&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp Sun Jan 21 21:54:46 2018
@@ -1054,8 +1054,8 @@ void SIRegisterInfo::eliminateFrameIndex
// Convert to an absolute stack address by finding the offset from the
// scratch wave base and scaling by the wave size.
//
- // In an entry function/kernel the stack address is already the absolute
- // address relative to the the scratch wave offset.
+ // In an entry function/kernel the stack address is already the
+ // absolute address relative to the scratch wave offset.
unsigned DiffReg
= MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h?rev=323074&r1=323073&r2=323074&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h Sun Jan 21 21:54:46 2018
@@ -122,8 +122,8 @@ public:
bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
MachineInstr *&CmpInst) const override;
- /// Generate code to reduce the loop iteration by one and check if the loop is
- /// finished. Return the value/register of the the new loop count. We need
+ /// Generate code to reduce the loop iteration by one and check if the loop
+ /// is finished. Return the value/register of the new loop count. We need
/// this function when peeling off one or more iterations of a loop. This
/// function assumes the nth iteration is peeled first.
unsigned reduceLoopCount(MachineBasicBlock &MBB,
Modified: llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp?rev=323074&r1=323073&r2=323074&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp Sun Jan 21 21:54:46 2018
@@ -628,7 +628,7 @@ void Liveness::computePhiInfo() {
// Collect the set PropUp of uses that are reached by the current
// phi PA, and are not covered by any intervening def between the
- // currently visited use UA and the the upward phi P.
+ // currently visited use UA and the upward phi P.
if (MidDefs.hasCoverOf(UR))
continue;
Modified: llvm/trunk/lib/Target/Lanai/LanaiInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiInstrFormats.td?rev=323074&r1=323073&r2=323074&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiInstrFormats.td Sun Jan 21 21:54:46 2018
@@ -482,7 +482,7 @@ class InstSLI<dag outs, dag ins, string
// Memory(ea) <- (least significant half-word of Rr)
// If `YS' = 10 (bYte load): Rr <- Memory(ea)
// If `YS' = 00 (halfword load): Rr <- Memory(ea)
-// [Note: here ea is determined as in the the RM instruction. ]
+// [Note: here ea is determined as in the RM instruction. ]
// If `SE' = 01 then the value is zEro extended
// before being loaded into Rd.
// If `SE' = 00 then the value is sign extended
Modified: llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp?rev=323074&r1=323073&r2=323074&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp Sun Jan 21 21:54:46 2018
@@ -632,7 +632,7 @@ bool Filler::runOnMachineBasicBlock(Mach
// TODO: Implement an instruction mapping table of 16bit opcodes to
// 32bit opcodes so that an instruction can be expanded. This would
// save 16 bits as a TAILCALL_MM pseudo requires a fullsized nop.
- // TODO: Permit b16 when branching backwards to the the same function
+ // TODO: Permit b16 when branching backwards to the same function
// if it is in range.
DSI->setDesc(TII->get(getEquivalentCallShort(DSI->getOpcode())));
}
Modified: llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp?rev=323074&r1=323073&r2=323074&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp Sun Jan 21 21:54:46 2018
@@ -288,7 +288,7 @@ void MipsSEDAGToDAGISel::selectAddE(SDNo
SDValue(Carry, 0)};
SDNode *DSPCFWithCarry = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, Ops);
- // My reading of the the MIPS DSP 3.01 specification isn't as clear as I
+ // My reading of the MIPS DSP 3.01 specification isn't as clear as I
// would like about whether bit 20 always gets overwritten by addwc.
// Hence take an extremely conservative view and presume it's sticky. We
// therefore need to clear it.
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