[llvm] r322989 - [SystemZ] Prefer LOCHI over generating IPM sequences
Ulrich Weigand via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 19 12:56:04 PST 2018
Author: uweigand
Date: Fri Jan 19 12:56:04 2018
New Revision: 322989
URL: http://llvm.org/viewvc/llvm-project?rev=322989&view=rev
Log:
[SystemZ] Prefer LOCHI over generating IPM sequences
On current machines we have load-on-condition instructions that can be
used to directly implement the SETCC semantics. If we have those, it is
always preferable to use them instead of generating the IPM sequence.
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
llvm/trunk/test/CodeGen/SystemZ/dag-combine-02.ll
llvm/trunk/test/CodeGen/SystemZ/vec-intrinsics-01.ll
llvm/trunk/test/CodeGen/SystemZ/vec-intrinsics-02.ll
Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp?rev=322989&r1=322988&r2=322989&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp Fri Jan 19 12:56:04 2018
@@ -1583,6 +1583,11 @@ SDValue SystemZDAGToDAGISel::expandSelec
}
void SystemZDAGToDAGISel::PreprocessISelDAG() {
+ // If we have conditional immediate loads, we always prefer
+ // using those over an IPM sequence.
+ if (Subtarget->hasLoadStoreOnCond2())
+ return;
+
bool MadeChange = false;
for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
Modified: llvm/trunk/test/CodeGen/SystemZ/dag-combine-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/dag-combine-02.ll?rev=322989&r1=322988&r2=322989&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/dag-combine-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/dag-combine-02.ll Fri Jan 19 12:56:04 2018
@@ -94,8 +94,8 @@ define signext i32 @main(i32 signext, i8
; <label>:61: ; preds = %13
; CHECK-LABEL: %bb.6:
-; CHECK: stgrl %r1, g_56
-; CHECK: llhrl %r1, g_56+6
+; CHECK: stgrl %r0, g_56
+; CHECK: llhrl %r0, g_56+6
; CHECK: stgrl %r2, g_56
store i64 0, i64* @g_56, align 8
%62 = bitcast [4 x [7 x i16*]]* %3 to i8*
Modified: llvm/trunk/test/CodeGen/SystemZ/vec-intrinsics-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/vec-intrinsics-01.ll?rev=322989&r1=322988&r2=322989&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/vec-intrinsics-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/vec-intrinsics-01.ll Fri Jan 19 12:56:04 2018
@@ -1736,9 +1736,8 @@ define i32 @test_vceqbs(<16 x i8> %a, <1
define i32 @test_vceqbs_any_bool(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vceqbs_any_bool:
; CHECK: vceqbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: afi %r2, -536870912
-; CHECK: srl %r2, 31
+; CHECK: lhi %r2, 0
+; CHECK: lochile %r2, 1
; CHECK: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vceqbs(<16 x i8> %a, <16 x i8> %b)
%res = extractvalue {<16 x i8>, i32} %call, 1
@@ -1785,8 +1784,8 @@ define i32 @test_vceqhs(<8 x i16> %a, <8
define i32 @test_vceqhs_notall_bool(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vceqhs_notall_bool:
; CHECK: vceqhs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: risblg %r2, [[REG]], 31, 159, 36
+; CHECK: lhi %r2, 0
+; CHECK: lochinhe %r2, 1
; CHECK: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vceqhs(<8 x i16> %a, <8 x i16> %b)
%res = extractvalue {<8 x i16>, i32} %call, 1
@@ -1834,8 +1833,8 @@ define i32 @test_vceqfs(<4 x i32> %a, <4
define i32 @test_vceqfs_none_bool(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vceqfs_none_bool:
; CHECK: vceqfs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: risblg %r2, [[REG]], 31, 159, 35
+; CHECK: lhi %r2, 0
+; CHECK: lochio %r2, 1
; CHECK: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vceqfs(<4 x i32> %a, <4 x i32> %b)
%res = extractvalue {<4 x i32>, i32} %call, 1
@@ -1883,9 +1882,8 @@ define i32 @test_vceqgs(<2 x i64> %a, <2
define i32 @test_vceqgs_all_bool(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vceqgs_all_bool:
; CHECK: vceqgs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: afi %r2, -268435456
-; CHECK: srl %r2, 31
+; CHECK: lhi %r2, 0
+; CHECK: lochie %r2, 1
; CHECK: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vceqgs(<2 x i64> %a, <2 x i64> %b)
%res = extractvalue {<2 x i64>, i32} %call, 1
@@ -1932,9 +1930,8 @@ define i32 @test_vchbs(<16 x i8> %a, <16
define i32 @test_vchbs_any_bool(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vchbs_any_bool:
; CHECK: vchbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: afi %r2, -536870912
-; CHECK: srl %r2, 31
+; CHECK: lhi %r2, 0
+; CHECK: lochile %r2, 1
; CHECK: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vchbs(<16 x i8> %a, <16 x i8> %b)
%res = extractvalue {<16 x i8>, i32} %call, 1
@@ -1981,8 +1978,8 @@ define i32 @test_vchhs(<8 x i16> %a, <8
define i32 @test_vchhs_notall_bool(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vchhs_notall_bool:
; CHECK: vchhs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: risblg %r2, [[REG]], 31, 159, 36
+; CHECK: lhi %r2, 0
+; CHECK: lochinhe %r2, 1
; CHECK: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vchhs(<8 x i16> %a, <8 x i16> %b)
%res = extractvalue {<8 x i16>, i32} %call, 1
@@ -2030,8 +2027,8 @@ define i32 @test_vchfs(<4 x i32> %a, <4
define i32 @test_vchfs_none_bool(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vchfs_none_bool:
; CHECK: vchfs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: risblg %r2, [[REG]], 31, 159, 35
+; CHECK: lhi %r2, 0
+; CHECK: lochio %r2, 1
; CHECK: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vchfs(<4 x i32> %a, <4 x i32> %b)
%res = extractvalue {<4 x i32>, i32} %call, 1
@@ -2078,9 +2075,8 @@ define i32 @test_vchgs(<2 x i64> %a, <2
define i32 @test_vchgs_all_bool(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vchgs_all_bool:
; CHECK: vchgs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: afi %r2, -268435456
-; CHECK: srl %r2, 31
+; CHECK: lhi %r2, 0
+; CHECK: lochie %r2, 1
; CHECK: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vchgs(<2 x i64> %a, <2 x i64> %b)
%res = extractvalue {<2 x i64>, i32} %call, 1
@@ -2127,9 +2123,8 @@ define i32 @test_vchlbs(<16 x i8> %a, <1
define i32 @test_vchlbs_any_bool(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vchlbs_any_bool:
; CHECK: vchlbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: afi %r2, -536870912
-; CHECK: srl %r2, 31
+; CHECK: lhi %r2, 0
+; CHECK: lochile %r2, 1
; CHECK: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vchlbs(<16 x i8> %a, <16 x i8> %b)
%res = extractvalue {<16 x i8>, i32} %call, 1
@@ -2176,8 +2171,8 @@ define i32 @test_vchlhs(<8 x i16> %a, <8
define i32 @test_vchlhs_notall_bool(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vchlhs_notall_bool:
; CHECK: vchlhs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: risblg %r2, [[REG]], 31, 159, 36
+; CHECK: lhi %r2, 0
+; CHECK: lochinhe %r2, 1
; CHECK: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vchlhs(<8 x i16> %a, <8 x i16> %b)
%res = extractvalue {<8 x i16>, i32} %call, 1
@@ -2225,8 +2220,8 @@ define i32 @test_vchlfs(<4 x i32> %a, <4
define i32 @test_vchlfs_none_bool(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vchlfs_none_bool:
; CHECK: vchlfs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: risblg %r2, [[REG]], 31, 159, 35
+; CHECK: lhi %r2, 0
+; CHECK: lochio %r2, 1
; CHECK: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vchlfs(<4 x i32> %a, <4 x i32> %b)
%res = extractvalue {<4 x i32>, i32} %call, 1
@@ -2274,9 +2269,8 @@ define i32 @test_vchlgs(<2 x i64> %a, <2
define i32 @test_vchlgs_all_bool(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vchlgs_all_bool:
; CHECK: vchlgs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: afi %r2, -268435456
-; CHECK: srl %r2, 31
+; CHECK: lhi %r2, 0
+; CHECK: lochie %r2, 1
; CHECK: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vchlgs(<2 x i64> %a, <2 x i64> %b)
%res = extractvalue {<2 x i64>, i32} %call, 1
@@ -3148,9 +3142,8 @@ define i32 @test_vfcedbs(<2 x double> %a
define i32 @test_vfcedbs_any_bool(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: test_vfcedbs_any_bool:
; CHECK: vfcedbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: afi %r2, -536870912
-; CHECK: srl %r2, 31
+; CHECK: lhi %r2, 0
+; CHECK: lochile %r2, 1
; CHECK: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vfcedbs(<2 x double> %a,
<2 x double> %b)
@@ -3201,8 +3194,8 @@ define i32 @test_vfchdbs(<2 x double> %a
define i32 @test_vfchdbs_notall_bool(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: test_vfchdbs_notall_bool:
; CHECK: vfchdbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: risblg %r2, [[REG]], 31, 159, 36
+; CHECK: lhi %r2, 0
+; CHECK: lochinhe %r2, 1
; CHECK: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vfchdbs(<2 x double> %a,
<2 x double> %b)
@@ -3253,8 +3246,8 @@ define i32 @test_vfchedbs(<2 x double> %
define i32 @test_vfchedbs_none_bool(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: test_vfchedbs_none_bool:
; CHECK: vfchedbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: risblg %r2, [[REG]], 31, 159, 35
+; CHECK: lhi %r2, 0
+; CHECK: lochio %r2, 1
; CHECK: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vfchedbs(<2 x double> %a,
<2 x double> %b)
@@ -3305,8 +3298,8 @@ define i32 @test_vftcidb(<2 x double> %a
define i32 @test_vftcidb_all_bool(<2 x double> %a) {
; CHECK-LABEL: test_vftcidb_all_bool:
; CHECK: vftcidb {{%v[0-9]+}}, %v24, 4094
-; CHECK: afi %r2, -268435456
-; CHECK: srl %r2, 31
+; CHECK: lhi %r2, 0
+; CHECK: lochie %r2, 1
; CHECK: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vftcidb(<2 x double> %a, i32 4094)
%res = extractvalue {<2 x i64>, i32} %call, 1
Modified: llvm/trunk/test/CodeGen/SystemZ/vec-intrinsics-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/vec-intrinsics-02.ll?rev=322989&r1=322988&r2=322989&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/vec-intrinsics-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/vec-intrinsics-02.ll Fri Jan 19 12:56:04 2018
@@ -218,9 +218,8 @@ define i32 @test_vfcesbs(<4 x float> %a,
define i32 @test_vfcesbs_any_bool(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: test_vfcesbs_any_bool:
; CHECK: vfcesbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: afi %r2, -536870912
-; CHECK: srl %r2, 31
+; CHECK: lhi %r2, 0
+; CHECK: lochile %r2, 1
; CHECK: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vfcesbs(<4 x float> %a,
<4 x float> %b)
@@ -271,8 +270,8 @@ define i32 @test_vfchsbs(<4 x float> %a,
define i32 @test_vfchsbs_notall_bool(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: test_vfchsbs_notall_bool:
; CHECK: vfchsbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: risblg %r2, [[REG]], 31, 159, 36
+; CHECK: lhi %r2, 0
+; CHECK: lochinhe %r2, 1
; CHECK: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vfchsbs(<4 x float> %a,
<4 x float> %b)
@@ -323,8 +322,8 @@ define i32 @test_vfchesbs(<4 x float> %a
define i32 @test_vfchesbs_none_bool(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: test_vfchesbs_none_bool:
; CHECK: vfchesbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: risblg %r2, [[REG]], 31, 159, 35
+; CHECK: lhi %r2, 0
+; CHECK: lochio %r2, 1
; CHECK: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vfchesbs(<4 x float> %a,
<4 x float> %b)
@@ -375,8 +374,8 @@ define i32 @test_vftcisb(<4 x float> %a)
define i32 @test_vftcisb_all_bool(<4 x float> %a) {
; CHECK-LABEL: test_vftcisb_all_bool:
; CHECK: vftcisb {{%v[0-9]+}}, %v24, 4094
-; CHECK: afi %r2, -268435456
-; CHECK: srl %r2, 31
+; CHECK: lhi %r2, 0
+; CHECK: lochie %r2, 1
; CHECK: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vftcisb(<4 x float> %a, i32 4094)
%res = extractvalue {<4 x i32>, i32} %call, 1
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