[PATCH] D42313: [X86] Don't reorder (srl (and X, C1), C2) if (and X, C1) can be matched as a movzx

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: spatel, RKSimon.

If we can match as a zero extend there's no need to flip the order to get an encoding benefit. As movzx is 3 bytes with independent source/dest registers. The shortest 'and' we could make is also 3 bytes unless we get lucky in the register allocator and its on AL/AX/EAX which have a 2 byte encoding.

This patch was more impressive before r322957 went in. It removed some of the same Ands that got deleted by that patch.


https://reviews.llvm.org/D42313

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/avx512bw-intrinsics-fast-isel.ll
  test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll

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