[PATCH] D42196: [compiler-rt] [builtins] Align addresses to cache lines in __clear_cache for aarch64

[Martin Storsjö via Phabricator via llvm-commits]

mstorsjo created this revision.
mstorsjo added reviewers: joerg, t.p.northover, compnerd.
Herald added subscribers: Sanitizers, kristof.beyls, dberris, rengolin, aemerson.

This makes sure that the last cache line gets invalidated properly.

This matches the example code at http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/BABJDBHI.html.


Repository:
  rCRT Compiler Runtime

https://reviews.llvm.org/D42196

Files:
  lib/builtins/clear_cache.c


Index: lib/builtins/clear_cache.c
===================================================================
--- lib/builtins/clear_cache.c
+++ lib/builtins/clear_cache.c
@@ -156,12 +156,14 @@
    * uintptr_t in case this runs in an IPL32 environment.
    */
   const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15);
-  for (addr = xstart; addr < xend; addr += dcache_line_size)
+  for (addr = xstart & ~(dcache_line_size - 1); addr < xend;
+       addr += dcache_line_size)
     __asm __volatile("dc cvau, %0" :: "r"(addr));
   __asm __volatile("dsb ish");
 
   const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15);
-  for (addr = xstart; addr < xend; addr += icache_line_size)
+  for (addr = xstart & ~(icache_line_size - 1); addr < xend;
+       addr += icache_line_size)
     __asm __volatile("ic ivau, %0" :: "r"(addr));
   __asm __volatile("isb sy");
 #elif defined (__powerpc64__)


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