[PATCH] D42033: [RISCV] Initial Machine Scheduler

[Leslie Zhai via Phabricator via llvm-commits]

xiangzhai added a comment.

Hi Alex,

Thanks for your response! Sorry that I borrow code from `ARMScheduleA9.td` which is of course not suitable for RISCV Target, and I only find some product introduction PDFs:

> And Rocket - RV64G - "in-order", single-issue applicaEon core, BOOM - RV64G - "out-of-order", superscalar applicaEon core https://riscv.org/wp-content/uploads/2016/01/Wed1345-RISCV-Workshop-3-BOOM.pdf

But where could I find the scheduling information providing "RV32 or RV64 Technical Reference Manual"? I am reading GCC riscv Target Generic DFA-based pipeline <https://github.com/gcc-mirror/gcc/blob/master/gcc/config/riscv/generic.md> but its comment indicated that:

> Based on MIPS target for GNU compiler.

So perhaps I can "migrate" GCC pipeline <https://gcc.gnu.org/onlinedocs/gccint/Processor-pipeline-description.html> to LLVM by reading GCC source code, if there is no manual?

Regards,
Leslie Zhai


Repository:
  rL LLVM

https://reviews.llvm.org/D42033