[llvm] r322839 - [RISCV] Implement frame pointer elimination
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 18 03:34:02 PST 2018
Author: asb
Date: Thu Jan 18 03:34:02 2018
New Revision: 322839
URL: http://llvm.org/viewvc/llvm-project?rev=322839&view=rev
Log:
[RISCV] Implement frame pointer elimination
Modified:
llvm/trunk/lib/Target/RISCV/RISCVFrameLowering.cpp
llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.cpp
llvm/trunk/test/CodeGen/RISCV/addc-adde-sube-subc.ll
llvm/trunk/test/CodeGen/RISCV/alu32.ll
llvm/trunk/test/CodeGen/RISCV/analyze-branch.ll
llvm/trunk/test/CodeGen/RISCV/bare-select.ll
llvm/trunk/test/CodeGen/RISCV/blockaddress.ll
llvm/trunk/test/CodeGen/RISCV/branch-relaxation.ll
llvm/trunk/test/CodeGen/RISCV/branch.ll
llvm/trunk/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
llvm/trunk/test/CodeGen/RISCV/byval.ll
llvm/trunk/test/CodeGen/RISCV/calling-conv-sext-zext.ll
llvm/trunk/test/CodeGen/RISCV/calling-conv.ll
llvm/trunk/test/CodeGen/RISCV/calls.ll
llvm/trunk/test/CodeGen/RISCV/div.ll
llvm/trunk/test/CodeGen/RISCV/fp128.ll
llvm/trunk/test/CodeGen/RISCV/frame.ll
llvm/trunk/test/CodeGen/RISCV/frameaddr-returnaddr.ll
llvm/trunk/test/CodeGen/RISCV/i32-icmp.ll
llvm/trunk/test/CodeGen/RISCV/imm.ll
llvm/trunk/test/CodeGen/RISCV/indirectbr.ll
llvm/trunk/test/CodeGen/RISCV/inline-asm.ll
llvm/trunk/test/CodeGen/RISCV/jumptable.ll
llvm/trunk/test/CodeGen/RISCV/large-stack.ll
llvm/trunk/test/CodeGen/RISCV/mem.ll
llvm/trunk/test/CodeGen/RISCV/mul.ll
llvm/trunk/test/CodeGen/RISCV/rem.ll
llvm/trunk/test/CodeGen/RISCV/rotl-rotr.ll
llvm/trunk/test/CodeGen/RISCV/select-cc.ll
llvm/trunk/test/CodeGen/RISCV/sext-zext-trunc.ll
llvm/trunk/test/CodeGen/RISCV/shifts.ll
llvm/trunk/test/CodeGen/RISCV/vararg.ll
llvm/trunk/test/CodeGen/RISCV/wide-mem.ll
Modified: llvm/trunk/lib/Target/RISCV/RISCVFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVFrameLowering.cpp?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVFrameLowering.cpp Thu Jan 18 03:34:02 2018
@@ -22,7 +22,14 @@
using namespace llvm;
-bool RISCVFrameLowering::hasFP(const MachineFunction &MF) const { return true; }
+bool RISCVFrameLowering::hasFP(const MachineFunction &MF) const {
+ const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
+
+ const MachineFrameInfo &MFI = MF.getFrameInfo();
+ return MF.getTarget().Options.DisableFramePointerElim(MF) ||
+ RegInfo->needsStackRealignment(MF) || MFI.hasVarSizedObjects() ||
+ MFI.isFrameAddressTaken();
+}
// Determines the size of the frame and maximum call frame size.
void RISCVFrameLowering::determineFrameLayout(MachineFunction &MF) const {
@@ -103,11 +110,6 @@ void RISCVFrameLowering::emitPrologue(Ma
MachineBasicBlock &MBB) const {
assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
- if (!hasFP(MF)) {
- report_fatal_error(
- "emitPrologue doesn't support framepointer-less functions");
- }
-
MachineFrameInfo &MFI = MF.getFrameInfo();
auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
MachineBasicBlock::iterator MBBI = MBB.begin();
@@ -143,17 +145,13 @@ void RISCVFrameLowering::emitPrologue(Ma
std::advance(MBBI, CSI.size());
// Generate new FP.
- adjustReg(MBB, MBBI, DL, FPReg, SPReg, StackSize - RVFI->getVarArgsSaveSize(),
- MachineInstr::FrameSetup);
+ if (hasFP(MF))
+ adjustReg(MBB, MBBI, DL, FPReg, SPReg,
+ StackSize - RVFI->getVarArgsSaveSize(), MachineInstr::FrameSetup);
}
void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
- if (!hasFP(MF)) {
- report_fatal_error(
- "emitEpilogue doesn't support framepointer-less functions");
- }
-
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
const RISCVRegisterInfo *RI = STI.getRegisterInfo();
MachineFrameInfo &MFI = MF.getFrameInfo();
@@ -174,6 +172,7 @@ void RISCVFrameLowering::emitEpilogue(Ma
// necessary if the stack pointer was modified, meaning the stack size is
// unknown.
if (RI->needsStackRealignment(MF) || MFI.hasVarSizedObjects()) {
+ assert(hasFP(MF) && "frame pointer should not have been eliminated");
adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg,
-StackSize + RVFI->getVarArgsSaveSize(),
MachineInstr::FrameDestroy);
@@ -210,8 +209,10 @@ int RISCVFrameLowering::getFrameIndexRef
Offset += MF.getFrameInfo().getStackSize();
} else {
FrameReg = RI->getFrameRegister(MF);
- assert(hasFP(MF) && "Offset calculation incorrect if !hasFP");
- Offset += RVFI->getVarArgsSaveSize();
+ if (hasFP(MF))
+ Offset += RVFI->getVarArgsSaveSize();
+ else
+ Offset += MF.getFrameInfo().getStackSize();
}
return Offset;
}
@@ -220,10 +221,12 @@ void RISCVFrameLowering::determineCallee
BitVector &SavedRegs,
RegScavenger *RS) const {
TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
- // TODO: Once frame pointer elimination is implemented, don't
- // unconditionally spill the frame pointer and return address.
- SavedRegs.set(RISCV::X1);
- SavedRegs.set(RISCV::X8);
+ // Unconditionally spill RA and FP only if the function uses a frame
+ // pointer.
+ if (hasFP(MF)) {
+ SavedRegs.set(RISCV::X1);
+ SavedRegs.set(RISCV::X8);
+ }
}
void RISCVFrameLowering::processFunctionBeforeFrameFinalized(
Modified: llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.cpp?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.cpp Thu Jan 18 03:34:02 2018
@@ -71,9 +71,6 @@ void RISCVRegisterInfo::eliminateFrameIn
getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) +
MI.getOperand(FIOperandNum + 1).getImm();
- assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) &&
- "eliminateFrameIndex currently requires hasFP");
-
if (!isInt<32>(Offset)) {
report_fatal_error(
"Frame offsets outside of the signed 32-bit range not supported");
@@ -102,7 +99,8 @@ void RISCVRegisterInfo::eliminateFrameIn
}
unsigned RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
- return RISCV::X8;
+ const TargetFrameLowering *TFI = getFrameLowering(MF);
+ return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
}
const uint32_t *
Modified: llvm/trunk/test/CodeGen/RISCV/addc-adde-sube-subc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/addc-adde-sube-subc.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/addc-adde-sube-subc.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/addc-adde-sube-subc.ll Thu Jan 18 03:34:02 2018
@@ -7,18 +7,11 @@
define i64 @addc_adde(i64 %a, i64 %b) {
; RV32I-LABEL: addc_adde:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: add a1, a1, a3
; RV32I-NEXT: add a2, a0, a2
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: add a1, a1, a0
; RV32I-NEXT: mv a0, a2
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = add i64 %a, %b
ret i64 %1
@@ -27,17 +20,10 @@ define i64 @addc_adde(i64 %a, i64 %b) {
define i64 @subc_sube(i64 %a, i64 %b) {
; RV32I-LABEL: subc_sube:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sub a1, a1, a3
; RV32I-NEXT: sltu a3, a0, a2
; RV32I-NEXT: sub a1, a1, a3
; RV32I-NEXT: sub a0, a0, a2
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = sub i64 %a, %b
ret i64 %1
Modified: llvm/trunk/test/CodeGen/RISCV/alu32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/alu32.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/alu32.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/alu32.ll Thu Jan 18 03:34:02 2018
@@ -11,14 +11,7 @@
define i32 @addi(i32 %a) nounwind {
; RV32I-LABEL: addi:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a0, a0, 1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = add i32 %a, 1
ret i32 %1
@@ -27,14 +20,7 @@ define i32 @addi(i32 %a) nounwind {
define i32 @slti(i32 %a) nounwind {
; RV32I-LABEL: slti:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slti a0, a0, 2
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp slt i32 %a, 2
%2 = zext i1 %1 to i32
@@ -44,14 +30,7 @@ define i32 @slti(i32 %a) nounwind {
define i32 @sltiu(i32 %a) nounwind {
; RV32I-LABEL: sltiu:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sltiu a0, a0, 3
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp ult i32 %a, 3
%2 = zext i1 %1 to i32
@@ -61,14 +40,7 @@ define i32 @sltiu(i32 %a) nounwind {
define i32 @xori(i32 %a) nounwind {
; RV32I-LABEL: xori:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: xori a0, a0, 4
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = xor i32 %a, 4
ret i32 %1
@@ -77,14 +49,7 @@ define i32 @xori(i32 %a) nounwind {
define i32 @ori(i32 %a) nounwind {
; RV32I-LABEL: ori:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: ori a0, a0, 5
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = or i32 %a, 5
ret i32 %1
@@ -93,14 +58,7 @@ define i32 @ori(i32 %a) nounwind {
define i32 @andi(i32 %a) nounwind {
; RV32I-LABEL: andi:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 6
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = and i32 %a, 6
ret i32 %1
@@ -109,14 +67,7 @@ define i32 @andi(i32 %a) nounwind {
define i32 @slli(i32 %a) nounwind {
; RV32I-LABEL: slli:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slli a0, a0, 7
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = shl i32 %a, 7
ret i32 %1
@@ -125,14 +76,7 @@ define i32 @slli(i32 %a) nounwind {
define i32 @srli(i32 %a) nounwind {
; RV32I-LABEL: srli:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: srli a0, a0, 8
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = lshr i32 %a, 8
ret i32 %1
@@ -141,14 +85,7 @@ define i32 @srli(i32 %a) nounwind {
define i32 @srai(i32 %a) nounwind {
; RV32I-LABEL: srai:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: srai a0, a0, 9
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = ashr i32 %a, 9
ret i32 %1
@@ -159,14 +96,7 @@ define i32 @srai(i32 %a) nounwind {
define i32 @add(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: add:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: add a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
@@ -175,14 +105,7 @@ define i32 @add(i32 %a, i32 %b) nounwind
define i32 @sub(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sub:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sub a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
@@ -191,14 +114,7 @@ define i32 @sub(i32 %a, i32 %b) nounwind
define i32 @sll(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sll:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sll a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
@@ -207,14 +123,7 @@ define i32 @sll(i32 %a, i32 %b) nounwind
define i32 @slt(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: slt:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slt a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp slt i32 %a, %b
%2 = zext i1 %1 to i32
@@ -224,14 +133,7 @@ define i32 @slt(i32 %a, i32 %b) nounwind
define i32 @sltu(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sltu:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sltu a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp ult i32 %a, %b
%2 = zext i1 %1 to i32
@@ -241,14 +143,7 @@ define i32 @sltu(i32 %a, i32 %b) nounwin
define i32 @xor(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: xor:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = xor i32 %a, %b
ret i32 %1
@@ -257,14 +152,7 @@ define i32 @xor(i32 %a, i32 %b) nounwind
define i32 @srl(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: srl:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: srl a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
@@ -273,14 +161,7 @@ define i32 @srl(i32 %a, i32 %b) nounwind
define i32 @sra(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sra:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sra a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
@@ -289,14 +170,7 @@ define i32 @sra(i32 %a, i32 %b) nounwind
define i32 @or(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: or:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: or a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = or i32 %a, %b
ret i32 %1
@@ -305,14 +179,7 @@ define i32 @or(i32 %a, i32 %b) nounwind
define i32 @and(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: and:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = and i32 %a, %b
ret i32 %1
Modified: llvm/trunk/test/CodeGen/RISCV/analyze-branch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/analyze-branch.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/analyze-branch.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/analyze-branch.ll Thu Jan 18 03:34:02 2018
@@ -17,8 +17,6 @@ define void @test_bcc_fallthrough_taken(
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a1, zero, 42
; RV32I-NEXT: bne a0, a1, .LBB0_3
; RV32I-NEXT: # %bb.1: # %true
@@ -26,7 +24,6 @@ define void @test_bcc_fallthrough_taken(
; RV32I-NEXT: addi a0, a0, %lo(test_true)
; RV32I-NEXT: .LBB0_2: # %true
; RV32I-NEXT: jalr a0
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -55,8 +52,6 @@ define void @test_bcc_fallthrough_nottak
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a1, zero, 42
; RV32I-NEXT: beq a0, a1, .LBB1_3
; RV32I-NEXT: # %bb.1: # %false
@@ -64,7 +59,6 @@ define void @test_bcc_fallthrough_nottak
; RV32I-NEXT: addi a0, a0, %lo(test_false)
; RV32I-NEXT: .LBB1_2: # %true
; RV32I-NEXT: jalr a0
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Modified: llvm/trunk/test/CodeGen/RISCV/bare-select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/bare-select.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/bare-select.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/bare-select.ll Thu Jan 18 03:34:02 2018
@@ -5,19 +5,12 @@
define i32 @bare_select(i1 %a, i32 %b, i32 %c) {
; RV32I-LABEL: bare_select:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: bnez a0, .LBB0_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: .LBB0_2:
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = select i1 %a, i32 %b, i32 %c
ret i32 %1
Modified: llvm/trunk/test/CodeGen/RISCV/blockaddress.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/blockaddress.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/blockaddress.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/blockaddress.ll Thu Jan 18 03:34:02 2018
@@ -9,8 +9,6 @@ define void @test_blockaddress() nounwin
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, %hi(addr)
; RV32I-NEXT: addi a0, a0, %lo(addr)
; RV32I-NEXT: lui a1, %hi(.Ltmp0)
@@ -20,7 +18,6 @@ define void @test_blockaddress() nounwin
; RV32I-NEXT: jr a0
; RV32I-NEXT: .Ltmp0: # Block address taken
; RV32I-NEXT: .LBB0_1: # %block
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Modified: llvm/trunk/test/CodeGen/RISCV/branch-relaxation.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/branch-relaxation.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/branch-relaxation.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/branch-relaxation.ll Thu Jan 18 03:34:02 2018
@@ -6,10 +6,6 @@
define void @relax_bcc(i1 %a) {
; CHECK-LABEL: relax_bcc:
; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw ra, 12(sp)
-; CHECK-NEXT: sw s0, 8(sp)
-; CHECK-NEXT: addi s0, sp, 16
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: bnez a0, .LBB0_1
; CHECK-NEXT: j .LBB0_2
@@ -18,9 +14,6 @@ define void @relax_bcc(i1 %a) {
; CHECK-NEXT: .space 4096
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB0_2: # %tail
-; CHECK-NEXT: lw s0, 8(sp)
-; CHECK-NEXT: lw ra, 12(sp)
-; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
br i1 %a, label %iftrue, label %tail
@@ -35,13 +28,9 @@ tail:
define i32 @relax_jal(i1 %a) {
; CHECK-LABEL: relax_jal:
; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw ra, 12(sp)
-; CHECK-NEXT: sw s0, 8(sp)
-; CHECK-NEXT: addi s0, sp, 16
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: bnez a0, .LBB1_1
-; CHECK-NEXT: # %bb.4:
+; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: lui a0, %hi(.LBB1_2)
; CHECK-NEXT: jalr zero, a0, %lo(.LBB1_2)
; CHECK-NEXT: .LBB1_1: # %iftrue
@@ -50,15 +39,12 @@ define i32 @relax_jal(i1 %a) {
; CHECK-NEXT: #APP
; CHECK-NEXT: .space 1048576
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: j .LBB1_3
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2: # %jmp
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB1_3: # %tail
; CHECK-NEXT: addi a0, zero, 1
-; CHECK-NEXT: lw s0, 8(sp)
-; CHECK-NEXT: lw ra, 12(sp)
-; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
br i1 %a, label %iftrue, label %jmp
Modified: llvm/trunk/test/CodeGen/RISCV/branch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/branch.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/branch.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/branch.ll Thu Jan 18 03:34:02 2018
@@ -5,10 +5,6 @@
define void @foo(i32 %a, i32 *%b, i1 %c) {
; RV32I-LABEL: foo:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: beq a3, a0, .LBB0_12
; RV32I-NEXT: # %bb.1: # %test2
@@ -45,9 +41,6 @@ define void @foo(i32 %a, i32 *%b, i1 %c)
; RV32I-NEXT: # %bb.11: # %test12
; RV32I-NEXT: lw a0, 0(a1)
; RV32I-NEXT: .LBB0_12: # %end
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%val1 = load volatile i32, i32* %b
Modified: llvm/trunk/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll Thu Jan 18 03:34:02 2018
@@ -15,10 +15,6 @@ declare i32 @llvm.ctpop.i32(i32)
define i16 @test_bswap_i16(i16 %a) nounwind {
; RV32I-LABEL: test_bswap_i16:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, 4080
; RV32I-NEXT: mv a1, a1
; RV32I-NEXT: slli a2, a0, 8
@@ -26,9 +22,6 @@ define i16 @test_bswap_i16(i16 %a) nounw
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a0, a0, 16
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%tmp = call i16 @llvm.bswap.i16(i16 %a)
ret i16 %tmp
@@ -37,10 +30,6 @@ define i16 @test_bswap_i16(i16 %a) nounw
define i32 @test_bswap_i32(i32 %a) nounwind {
; RV32I-LABEL: test_bswap_i32:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -256
; RV32I-NEXT: srli a2, a0, 8
@@ -54,9 +43,6 @@ define i32 @test_bswap_i32(i32 %a) nounw
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%tmp = call i32 @llvm.bswap.i32(i32 %a)
ret i32 %tmp
@@ -65,10 +51,6 @@ define i32 @test_bswap_i32(i32 %a) nounw
define i64 @test_bswap_i64(i64 %a) nounwind {
; RV32I-LABEL: test_bswap_i64:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a3, a2, -256
; RV32I-NEXT: srli a2, a1, 8
@@ -92,9 +74,6 @@ define i64 @test_bswap_i64(i64 %a) nounw
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a1, a0, a1
; RV32I-NEXT: mv a0, a2
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%tmp = call i64 @llvm.bswap.i64(i64 %a)
ret i64 %tmp
@@ -105,8 +84,6 @@ define i8 @test_cttz_i8(i8 %a) nounwind
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a1, a0, 255
; RV32I-NEXT: beqz a1, .LBB3_2
; RV32I-NEXT: # %bb.1: # %cond.false
@@ -139,7 +116,6 @@ define i8 @test_cttz_i8(i8 %a) nounwind
; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: addi a0, zero, 8
; RV32I-NEXT: .LBB3_3: # %cond.end
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -152,8 +128,6 @@ define i16 @test_cttz_i16(i16 %a) nounwi
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a1, a0, a1
@@ -188,7 +162,6 @@ define i16 @test_cttz_i16(i16 %a) nounwi
; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: addi a0, zero, 16
; RV32I-NEXT: .LBB4_3: # %cond.end
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -201,8 +174,6 @@ define i32 @test_cttz_i32(i32 %a) nounwi
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: beqz a0, .LBB5_2
; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi a1, a0, -1
@@ -234,7 +205,6 @@ define i32 @test_cttz_i32(i32 %a) nounwi
; RV32I-NEXT: .LBB5_2:
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: .LBB5_3: # %cond.end
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -247,8 +217,6 @@ define i32 @test_ctlz_i32(i32 %a) nounwi
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: beqz a0, .LBB6_2
; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: srli a1, a0, 1
@@ -288,7 +256,6 @@ define i32 @test_ctlz_i32(i32 %a) nounwi
; RV32I-NEXT: .LBB6_2:
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: .LBB6_3: # %cond.end
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -301,16 +268,14 @@ define i64 @test_cttz_i64(i64 %a) nounwi
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp)
-; RV32I-NEXT: sw s0, 40(sp)
-; RV32I-NEXT: sw s1, 36(sp)
-; RV32I-NEXT: sw s2, 32(sp)
-; RV32I-NEXT: sw s3, 28(sp)
-; RV32I-NEXT: sw s4, 24(sp)
-; RV32I-NEXT: sw s5, 20(sp)
-; RV32I-NEXT: sw s6, 16(sp)
-; RV32I-NEXT: sw s7, 12(sp)
-; RV32I-NEXT: sw s8, 8(sp)
-; RV32I-NEXT: addi s0, sp, 48
+; RV32I-NEXT: sw s1, 40(sp)
+; RV32I-NEXT: sw s2, 36(sp)
+; RV32I-NEXT: sw s3, 32(sp)
+; RV32I-NEXT: sw s4, 28(sp)
+; RV32I-NEXT: sw s5, 24(sp)
+; RV32I-NEXT: sw s6, 20(sp)
+; RV32I-NEXT: sw s7, 16(sp)
+; RV32I-NEXT: sw s8, 12(sp)
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: addi a0, s3, -1
@@ -363,15 +328,14 @@ define i64 @test_cttz_i64(i64 %a) nounwi
; RV32I-NEXT: srli a0, s1, 24
; RV32I-NEXT: .LBB7_3:
; RV32I-NEXT: mv a1, zero
-; RV32I-NEXT: lw s8, 8(sp)
-; RV32I-NEXT: lw s7, 12(sp)
-; RV32I-NEXT: lw s6, 16(sp)
-; RV32I-NEXT: lw s5, 20(sp)
-; RV32I-NEXT: lw s4, 24(sp)
-; RV32I-NEXT: lw s3, 28(sp)
-; RV32I-NEXT: lw s2, 32(sp)
-; RV32I-NEXT: lw s1, 36(sp)
-; RV32I-NEXT: lw s0, 40(sp)
+; RV32I-NEXT: lw s8, 12(sp)
+; RV32I-NEXT: lw s7, 16(sp)
+; RV32I-NEXT: lw s6, 20(sp)
+; RV32I-NEXT: lw s5, 24(sp)
+; RV32I-NEXT: lw s4, 28(sp)
+; RV32I-NEXT: lw s3, 32(sp)
+; RV32I-NEXT: lw s2, 36(sp)
+; RV32I-NEXT: lw s1, 40(sp)
; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret
@@ -384,8 +348,6 @@ define i8 @test_cttz_i8_zero_undef(i8 %a
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
@@ -411,7 +373,6 @@ define i8 @test_cttz_i8_zero_undef(i8 %a
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
; RV32I-NEXT: jalr a2
; RV32I-NEXT: srli a0, a0, 24
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -424,8 +385,6 @@ define i16 @test_cttz_i16_zero_undef(i16
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
@@ -451,7 +410,6 @@ define i16 @test_cttz_i16_zero_undef(i16
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
; RV32I-NEXT: jalr a2
; RV32I-NEXT: srli a0, a0, 24
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -464,8 +422,6 @@ define i32 @test_cttz_i32_zero_undef(i32
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
@@ -491,7 +447,6 @@ define i32 @test_cttz_i32_zero_undef(i32
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
; RV32I-NEXT: jalr a2
; RV32I-NEXT: srli a0, a0, 24
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -504,16 +459,14 @@ define i64 @test_cttz_i64_zero_undef(i64
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp)
-; RV32I-NEXT: sw s0, 40(sp)
-; RV32I-NEXT: sw s1, 36(sp)
-; RV32I-NEXT: sw s2, 32(sp)
-; RV32I-NEXT: sw s3, 28(sp)
-; RV32I-NEXT: sw s4, 24(sp)
-; RV32I-NEXT: sw s5, 20(sp)
-; RV32I-NEXT: sw s6, 16(sp)
-; RV32I-NEXT: sw s7, 12(sp)
-; RV32I-NEXT: sw s8, 8(sp)
-; RV32I-NEXT: addi s0, sp, 48
+; RV32I-NEXT: sw s1, 40(sp)
+; RV32I-NEXT: sw s2, 36(sp)
+; RV32I-NEXT: sw s3, 32(sp)
+; RV32I-NEXT: sw s4, 28(sp)
+; RV32I-NEXT: sw s5, 24(sp)
+; RV32I-NEXT: sw s6, 20(sp)
+; RV32I-NEXT: sw s7, 16(sp)
+; RV32I-NEXT: sw s8, 12(sp)
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: addi a0, s3, -1
@@ -566,15 +519,14 @@ define i64 @test_cttz_i64_zero_undef(i64
; RV32I-NEXT: srli a0, s1, 24
; RV32I-NEXT: .LBB11_3:
; RV32I-NEXT: mv a1, zero
-; RV32I-NEXT: lw s8, 8(sp)
-; RV32I-NEXT: lw s7, 12(sp)
-; RV32I-NEXT: lw s6, 16(sp)
-; RV32I-NEXT: lw s5, 20(sp)
-; RV32I-NEXT: lw s4, 24(sp)
-; RV32I-NEXT: lw s3, 28(sp)
-; RV32I-NEXT: lw s2, 32(sp)
-; RV32I-NEXT: lw s1, 36(sp)
-; RV32I-NEXT: lw s0, 40(sp)
+; RV32I-NEXT: lw s8, 12(sp)
+; RV32I-NEXT: lw s7, 16(sp)
+; RV32I-NEXT: lw s6, 20(sp)
+; RV32I-NEXT: lw s5, 24(sp)
+; RV32I-NEXT: lw s4, 28(sp)
+; RV32I-NEXT: lw s3, 32(sp)
+; RV32I-NEXT: lw s2, 36(sp)
+; RV32I-NEXT: lw s1, 40(sp)
; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret
@@ -587,8 +539,6 @@ define i32 @test_ctpop_i32(i32 %a) nounw
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi a1, a1, 1365
; RV32I-NEXT: srli a2, a0, 1
@@ -611,7 +561,6 @@ define i32 @test_ctpop_i32(i32 %a) nounw
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
; RV32I-NEXT: jalr a2
; RV32I-NEXT: srli a0, a0, 24
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Modified: llvm/trunk/test/CodeGen/RISCV/byval.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/byval.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/byval.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/byval.ll Thu Jan 18 03:34:02 2018
@@ -8,14 +8,7 @@
define i32 @callee(%struct.Foo* byval %f) nounwind {
; RV32I-LABEL: callee:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
entry:
%0 = getelementptr inbounds %struct.Foo, %struct.Foo* %f, i32 0, i32 0
@@ -29,29 +22,26 @@ define void @caller() nounwind {
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: addi s0, sp, 32
; RV32I-NEXT: lui a0, %hi(foo+12)
; RV32I-NEXT: addi a0, a0, %lo(foo+12)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -12(s0)
+; RV32I-NEXT: sw a0, 24(sp)
; RV32I-NEXT: lui a0, %hi(foo+8)
; RV32I-NEXT: addi a0, a0, %lo(foo+8)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -16(s0)
+; RV32I-NEXT: sw a0, 20(sp)
; RV32I-NEXT: lui a0, %hi(foo+4)
; RV32I-NEXT: addi a0, a0, %lo(foo+4)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -20(s0)
+; RV32I-NEXT: sw a0, 16(sp)
; RV32I-NEXT: lui a0, %hi(foo)
; RV32I-NEXT: addi a0, a0, %lo(foo)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -24(s0)
+; RV32I-NEXT: sw a0, 12(sp)
; RV32I-NEXT: lui a0, %hi(callee)
; RV32I-NEXT: addi a1, a0, %lo(callee)
-; RV32I-NEXT: addi a0, s0, -24
+; RV32I-NEXT: addi a0, sp, 12
; RV32I-NEXT: jalr a1
-; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
Modified: llvm/trunk/test/CodeGen/RISCV/calling-conv-sext-zext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/calling-conv-sext-zext.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/calling-conv-sext-zext.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/calling-conv-sext-zext.ll Thu Jan 18 03:34:02 2018
@@ -5,13 +5,6 @@
define zeroext i8 @uint8_arg_to_uint8_ret(i8 zeroext %a) nounwind {
; RV32I-LABEL: uint8_arg_to_uint8_ret:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
ret i8 %a
}
@@ -23,12 +16,9 @@ define void @pass_uint8_as_uint8(i8 zero
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(receive_uint8)
; RV32I-NEXT: addi a1, a1, %lo(receive_uint8)
; RV32I-NEXT: jalr a1
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -43,12 +33,9 @@ define zeroext i8 @ret_callresult_uint8_
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, %hi(return_uint8)
; RV32I-NEXT: addi a0, a0, %lo(return_uint8)
; RV32I-NEXT: jalr a0
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -59,15 +46,8 @@ define zeroext i8 @ret_callresult_uint8_
define signext i8 @uint8_arg_to_sint8_ret(i8 zeroext %a) nounwind {
; RV32I-LABEL: uint8_arg_to_sint8_ret:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
ret i8 %a
}
@@ -79,14 +59,11 @@ define void @pass_uint8_as_sint8(i8 zero
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(receive_sint8)
; RV32I-NEXT: addi a1, a1, %lo(receive_sint8)
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: jalr a1
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -100,14 +77,11 @@ define signext i8 @ret_callresult_uint8_
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, %hi(return_uint8)
; RV32I-NEXT: addi a0, a0, %lo(return_uint8)
; RV32I-NEXT: jalr a0
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -118,13 +92,6 @@ define signext i8 @ret_callresult_uint8_
define signext i32 @uint8_arg_to_anyint32_ret(i8 zeroext %a) nounwind {
; RV32I-LABEL: uint8_arg_to_anyint32_ret:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = zext i8 %a to i32
ret i32 %1
@@ -137,12 +104,9 @@ define void @pass_uint8_as_anyint32(i8 z
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(receive_anyint32)
; RV32I-NEXT: addi a1, a1, %lo(receive_anyint32)
; RV32I-NEXT: jalr a1
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -156,12 +120,9 @@ define signext i32 @ret_callresult_uint8
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, %hi(return_uint8)
; RV32I-NEXT: addi a0, a0, %lo(return_uint8)
; RV32I-NEXT: jalr a0
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -173,14 +134,7 @@ define signext i32 @ret_callresult_uint8
define zeroext i8 @sint8_arg_to_uint8_ret(i8 signext %a) nounwind {
; RV32I-LABEL: sint8_arg_to_uint8_ret:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 255
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
ret i8 %a
}
@@ -190,13 +144,10 @@ define void @pass_sint8_as_uint8(i8 sign
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: lui a1, %hi(receive_uint8)
; RV32I-NEXT: addi a1, a1, %lo(receive_uint8)
; RV32I-NEXT: jalr a1
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -211,13 +162,10 @@ define zeroext i8 @ret_callresult_sint8_
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, %hi(return_sint8)
; RV32I-NEXT: addi a0, a0, %lo(return_sint8)
; RV32I-NEXT: jalr a0
; RV32I-NEXT: andi a0, a0, 255
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -228,13 +176,6 @@ define zeroext i8 @ret_callresult_sint8_
define signext i8 @sint8_arg_to_sint8_ret(i8 signext %a) nounwind {
; RV32I-LABEL: sint8_arg_to_sint8_ret:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
ret i8 %a
}
@@ -244,12 +185,9 @@ define void @pass_sint8_as_sint8(i8 sign
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(receive_sint8)
; RV32I-NEXT: addi a1, a1, %lo(receive_sint8)
; RV32I-NEXT: jalr a1
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -262,12 +200,9 @@ define signext i8 @ret_callresult_sint8_
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, %hi(return_sint8)
; RV32I-NEXT: addi a0, a0, %lo(return_sint8)
; RV32I-NEXT: jalr a0
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -278,13 +213,6 @@ define signext i8 @ret_callresult_sint8_
define signext i32 @sint8_arg_to_anyint32_ret(i8 signext %a) nounwind {
; RV32I-LABEL: sint8_arg_to_anyint32_ret:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = sext i8 %a to i32
ret i32 %1
@@ -295,12 +223,9 @@ define void @pass_sint8_as_anyint32(i8 s
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(receive_anyint32)
; RV32I-NEXT: addi a1, a1, %lo(receive_anyint32)
; RV32I-NEXT: jalr a1
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -314,12 +239,9 @@ define signext i32 @ret_callresult_sint8
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, %hi(return_sint8)
; RV32I-NEXT: addi a0, a0, %lo(return_sint8)
; RV32I-NEXT: jalr a0
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -331,14 +253,7 @@ define signext i32 @ret_callresult_sint8
define zeroext i8 @anyint32_arg_to_uint8_ret(i32 signext %a) nounwind {
; RV32I-LABEL: anyint32_arg_to_uint8_ret:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 255
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = trunc i32 %a to i8
ret i8 %1
@@ -349,13 +264,10 @@ define void @pass_anyint32_as_uint8(i32
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: lui a1, %hi(receive_uint8)
; RV32I-NEXT: addi a1, a1, %lo(receive_uint8)
; RV32I-NEXT: jalr a1
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -371,13 +283,10 @@ define zeroext i8 @ret_callresult_anyint
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, %hi(return_anyint32)
; RV32I-NEXT: addi a0, a0, %lo(return_anyint32)
; RV32I-NEXT: jalr a0
; RV32I-NEXT: andi a0, a0, 255
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -389,15 +298,8 @@ define zeroext i8 @ret_callresult_anyint
define signext i8 @anyint32_arg_to_sint8_ret(i32 signext %a) nounwind {
; RV32I-LABEL: anyint32_arg_to_sint8_ret:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = trunc i32 %a to i8
ret i8 %1
@@ -408,14 +310,11 @@ define void @pass_anyint32_as_sint8(i32
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(receive_sint8)
; RV32I-NEXT: addi a1, a1, %lo(receive_sint8)
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: jalr a1
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -429,14 +328,11 @@ define signext i8 @ret_callresult_anyint
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, %hi(return_anyint32)
; RV32I-NEXT: addi a0, a0, %lo(return_anyint32)
; RV32I-NEXT: jalr a0
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -448,13 +344,6 @@ define signext i8 @ret_callresult_anyint
define signext i32 @anyint32_arg_to_anyint32_ret(i32 signext %a) nounwind {
; RV32I-LABEL: anyint32_arg_to_anyint32_ret:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
ret i32 %a
}
@@ -464,12 +353,9 @@ define void @pass_anyint32_as_anyint32(i
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(receive_anyint32)
; RV32I-NEXT: addi a1, a1, %lo(receive_anyint32)
; RV32I-NEXT: jalr a1
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -482,12 +368,9 @@ define signext i32 @ret_callresult_anyin
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, %hi(return_anyint32)
; RV32I-NEXT: addi a0, a0, %lo(return_anyint32)
; RV32I-NEXT: jalr a0
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Modified: llvm/trunk/test/CodeGen/RISCV/calling-conv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/calling-conv.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/calling-conv.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/calling-conv.ll Thu Jan 18 03:34:02 2018
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs -disable-fp-elim < %s \
+; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s
; As well as calling convention details, we check that ra and fp are
; consistently stored to fp-4 and fp-8.
@@ -9,37 +11,66 @@
; the convention for varargs, this need not be an aligned pair.
define i32 @callee_scalars(i32 %a, i64 %b, i32 %c, i32 %d, double %e) nounwind {
-; RV32I-LABEL: callee_scalars:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
-; RV32I-NEXT: sw s4, 8(sp)
-; RV32I-NEXT: addi s0, sp, 32
-; RV32I-NEXT: mv s1, a4
-; RV32I-NEXT: mv s2, a3
-; RV32I-NEXT: mv s3, a1
-; RV32I-NEXT: mv s4, a0
-; RV32I-NEXT: lui a0, %hi(__fixdfsi)
-; RV32I-NEXT: addi a2, a0, %lo(__fixdfsi)
-; RV32I-NEXT: mv a0, a5
-; RV32I-NEXT: mv a1, a6
-; RV32I-NEXT: jalr a2
-; RV32I-NEXT: add a1, s4, s3
-; RV32I-NEXT: add a1, a1, s2
-; RV32I-NEXT: add a1, a1, s1
-; RV32I-NEXT: add a0, a1, a0
-; RV32I-NEXT: lw s4, 8(sp)
-; RV32I-NEXT: lw s3, 12(sp)
-; RV32I-NEXT: lw s2, 16(sp)
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: callee_scalars:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -32
+; RV32I-FPELIM-NEXT: sw ra, 28(sp)
+; RV32I-FPELIM-NEXT: sw s1, 24(sp)
+; RV32I-FPELIM-NEXT: sw s2, 20(sp)
+; RV32I-FPELIM-NEXT: sw s3, 16(sp)
+; RV32I-FPELIM-NEXT: sw s4, 12(sp)
+; RV32I-FPELIM-NEXT: mv s1, a4
+; RV32I-FPELIM-NEXT: mv s2, a3
+; RV32I-FPELIM-NEXT: mv s3, a1
+; RV32I-FPELIM-NEXT: mv s4, a0
+; RV32I-FPELIM-NEXT: lui a0, %hi(__fixdfsi)
+; RV32I-FPELIM-NEXT: addi a2, a0, %lo(__fixdfsi)
+; RV32I-FPELIM-NEXT: mv a0, a5
+; RV32I-FPELIM-NEXT: mv a1, a6
+; RV32I-FPELIM-NEXT: jalr a2
+; RV32I-FPELIM-NEXT: add a1, s4, s3
+; RV32I-FPELIM-NEXT: add a1, a1, s2
+; RV32I-FPELIM-NEXT: add a1, a1, s1
+; RV32I-FPELIM-NEXT: add a0, a1, a0
+; RV32I-FPELIM-NEXT: lw s4, 12(sp)
+; RV32I-FPELIM-NEXT: lw s3, 16(sp)
+; RV32I-FPELIM-NEXT: lw s2, 20(sp)
+; RV32I-FPELIM-NEXT: lw s1, 24(sp)
+; RV32I-FPELIM-NEXT: lw ra, 28(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 32
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: callee_scalars:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -32
+; RV32I-WITHFP-NEXT: sw ra, 28(sp)
+; RV32I-WITHFP-NEXT: sw s0, 24(sp)
+; RV32I-WITHFP-NEXT: sw s1, 20(sp)
+; RV32I-WITHFP-NEXT: sw s2, 16(sp)
+; RV32I-WITHFP-NEXT: sw s3, 12(sp)
+; RV32I-WITHFP-NEXT: sw s4, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 32
+; RV32I-WITHFP-NEXT: mv s1, a4
+; RV32I-WITHFP-NEXT: mv s2, a3
+; RV32I-WITHFP-NEXT: mv s3, a1
+; RV32I-WITHFP-NEXT: mv s4, a0
+; RV32I-WITHFP-NEXT: lui a0, %hi(__fixdfsi)
+; RV32I-WITHFP-NEXT: addi a2, a0, %lo(__fixdfsi)
+; RV32I-WITHFP-NEXT: mv a0, a5
+; RV32I-WITHFP-NEXT: mv a1, a6
+; RV32I-WITHFP-NEXT: jalr a2
+; RV32I-WITHFP-NEXT: add a1, s4, s3
+; RV32I-WITHFP-NEXT: add a1, a1, s2
+; RV32I-WITHFP-NEXT: add a1, a1, s1
+; RV32I-WITHFP-NEXT: add a0, a1, a0
+; RV32I-WITHFP-NEXT: lw s4, 8(sp)
+; RV32I-WITHFP-NEXT: lw s3, 12(sp)
+; RV32I-WITHFP-NEXT: lw s2, 16(sp)
+; RV32I-WITHFP-NEXT: lw s1, 20(sp)
+; RV32I-WITHFP-NEXT: lw s0, 24(sp)
+; RV32I-WITHFP-NEXT: lw ra, 28(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 32
+; RV32I-WITHFP-NEXT: ret
%b_trunc = trunc i64 %b to i32
%e_fptosi = fptosi double %e to i32
%1 = add i32 %a, %b_trunc
@@ -50,27 +81,46 @@ define i32 @callee_scalars(i32 %a, i64 %
}
define i32 @caller_scalars() nounwind {
-; RV32I-LABEL: caller_scalars:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lui a0, 262464
-; RV32I-NEXT: mv a6, a0
-; RV32I-NEXT: lui a0, %hi(callee_scalars)
-; RV32I-NEXT: addi a7, a0, %lo(callee_scalars)
-; RV32I-NEXT: addi a0, zero, 1
-; RV32I-NEXT: addi a1, zero, 2
-; RV32I-NEXT: addi a3, zero, 3
-; RV32I-NEXT: addi a4, zero, 4
-; RV32I-NEXT: mv a2, zero
-; RV32I-NEXT: mv a5, zero
-; RV32I-NEXT: jalr a7
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: caller_scalars:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -16
+; RV32I-FPELIM-NEXT: sw ra, 12(sp)
+; RV32I-FPELIM-NEXT: lui a0, 262464
+; RV32I-FPELIM-NEXT: mv a6, a0
+; RV32I-FPELIM-NEXT: lui a0, %hi(callee_scalars)
+; RV32I-FPELIM-NEXT: addi a7, a0, %lo(callee_scalars)
+; RV32I-FPELIM-NEXT: addi a0, zero, 1
+; RV32I-FPELIM-NEXT: addi a1, zero, 2
+; RV32I-FPELIM-NEXT: addi a3, zero, 3
+; RV32I-FPELIM-NEXT: addi a4, zero, 4
+; RV32I-FPELIM-NEXT: mv a2, zero
+; RV32I-FPELIM-NEXT: mv a5, zero
+; RV32I-FPELIM-NEXT: jalr a7
+; RV32I-FPELIM-NEXT: lw ra, 12(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 16
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: caller_scalars:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -16
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: lui a0, 262464
+; RV32I-WITHFP-NEXT: mv a6, a0
+; RV32I-WITHFP-NEXT: lui a0, %hi(callee_scalars)
+; RV32I-WITHFP-NEXT: addi a7, a0, %lo(callee_scalars)
+; RV32I-WITHFP-NEXT: addi a0, zero, 1
+; RV32I-WITHFP-NEXT: addi a1, zero, 2
+; RV32I-WITHFP-NEXT: addi a3, zero, 3
+; RV32I-WITHFP-NEXT: addi a4, zero, 4
+; RV32I-WITHFP-NEXT: mv a2, zero
+; RV32I-WITHFP-NEXT: mv a5, zero
+; RV32I-WITHFP-NEXT: jalr a7
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 16
+; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_scalars(i32 1, i64 2, i32 3, i32 4, double 5.000000e+00)
ret i32 %1
}
@@ -78,33 +128,54 @@ define i32 @caller_scalars() nounwind {
; Check that i128 and fp128 are passed indirectly
define i32 @callee_large_scalars(i128 %a, fp128 %b) nounwind {
-; RV32I-LABEL: callee_large_scalars:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lw a2, 12(a1)
-; RV32I-NEXT: lw a3, 12(a0)
-; RV32I-NEXT: xor a2, a3, a2
-; RV32I-NEXT: lw a3, 4(a1)
-; RV32I-NEXT: lw a4, 4(a0)
-; RV32I-NEXT: xor a3, a4, a3
-; RV32I-NEXT: or a2, a3, a2
-; RV32I-NEXT: lw a3, 8(a1)
-; RV32I-NEXT: lw a4, 8(a0)
-; RV32I-NEXT: xor a3, a4, a3
-; RV32I-NEXT: lw a1, 0(a1)
-; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: or a0, a0, a3
-; RV32I-NEXT: or a0, a0, a2
-; RV32I-NEXT: xor a0, a0, zero
-; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: callee_large_scalars:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: lw a2, 12(a1)
+; RV32I-FPELIM-NEXT: lw a3, 12(a0)
+; RV32I-FPELIM-NEXT: xor a2, a3, a2
+; RV32I-FPELIM-NEXT: lw a3, 4(a1)
+; RV32I-FPELIM-NEXT: lw a4, 4(a0)
+; RV32I-FPELIM-NEXT: xor a3, a4, a3
+; RV32I-FPELIM-NEXT: or a2, a3, a2
+; RV32I-FPELIM-NEXT: lw a3, 8(a1)
+; RV32I-FPELIM-NEXT: lw a4, 8(a0)
+; RV32I-FPELIM-NEXT: xor a3, a4, a3
+; RV32I-FPELIM-NEXT: lw a1, 0(a1)
+; RV32I-FPELIM-NEXT: lw a0, 0(a0)
+; RV32I-FPELIM-NEXT: xor a0, a0, a1
+; RV32I-FPELIM-NEXT: or a0, a0, a3
+; RV32I-FPELIM-NEXT: or a0, a0, a2
+; RV32I-FPELIM-NEXT: xor a0, a0, zero
+; RV32I-FPELIM-NEXT: seqz a0, a0
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: callee_large_scalars:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -16
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: lw a2, 12(a1)
+; RV32I-WITHFP-NEXT: lw a3, 12(a0)
+; RV32I-WITHFP-NEXT: xor a2, a3, a2
+; RV32I-WITHFP-NEXT: lw a3, 4(a1)
+; RV32I-WITHFP-NEXT: lw a4, 4(a0)
+; RV32I-WITHFP-NEXT: xor a3, a4, a3
+; RV32I-WITHFP-NEXT: or a2, a3, a2
+; RV32I-WITHFP-NEXT: lw a3, 8(a1)
+; RV32I-WITHFP-NEXT: lw a4, 8(a0)
+; RV32I-WITHFP-NEXT: xor a3, a4, a3
+; RV32I-WITHFP-NEXT: lw a1, 0(a1)
+; RV32I-WITHFP-NEXT: lw a0, 0(a0)
+; RV32I-WITHFP-NEXT: xor a0, a0, a1
+; RV32I-WITHFP-NEXT: or a0, a0, a3
+; RV32I-WITHFP-NEXT: or a0, a0, a2
+; RV32I-WITHFP-NEXT: xor a0, a0, zero
+; RV32I-WITHFP-NEXT: seqz a0, a0
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 16
+; RV32I-WITHFP-NEXT: ret
%b_bitcast = bitcast fp128 %b to i128
%1 = icmp eq i128 %a, %b_bitcast
%2 = zext i1 %1 to i32
@@ -112,32 +183,56 @@ define i32 @callee_large_scalars(i128 %a
}
define i32 @caller_large_scalars() nounwind {
-; RV32I-LABEL: caller_large_scalars:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -48
-; RV32I-NEXT: sw ra, 44(sp)
-; RV32I-NEXT: sw s0, 40(sp)
-; RV32I-NEXT: addi s0, sp, 48
-; RV32I-NEXT: sw zero, -40(s0)
-; RV32I-NEXT: sw zero, -44(s0)
-; RV32I-NEXT: sw zero, -48(s0)
-; RV32I-NEXT: sw zero, -12(s0)
-; RV32I-NEXT: sw zero, -16(s0)
-; RV32I-NEXT: sw zero, -20(s0)
-; RV32I-NEXT: addi a0, zero, 1
-; RV32I-NEXT: sw a0, -24(s0)
-; RV32I-NEXT: lui a0, 524272
-; RV32I-NEXT: mv a0, a0
-; RV32I-NEXT: sw a0, -36(s0)
-; RV32I-NEXT: lui a0, %hi(callee_large_scalars)
-; RV32I-NEXT: addi a2, a0, %lo(callee_large_scalars)
-; RV32I-NEXT: addi a0, s0, -24
-; RV32I-NEXT: addi a1, s0, -48
-; RV32I-NEXT: jalr a2
-; RV32I-NEXT: lw s0, 40(sp)
-; RV32I-NEXT: lw ra, 44(sp)
-; RV32I-NEXT: addi sp, sp, 48
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: caller_large_scalars:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -48
+; RV32I-FPELIM-NEXT: sw ra, 44(sp)
+; RV32I-FPELIM-NEXT: sw zero, 8(sp)
+; RV32I-FPELIM-NEXT: sw zero, 4(sp)
+; RV32I-FPELIM-NEXT: sw zero, 0(sp)
+; RV32I-FPELIM-NEXT: sw zero, 36(sp)
+; RV32I-FPELIM-NEXT: sw zero, 32(sp)
+; RV32I-FPELIM-NEXT: sw zero, 28(sp)
+; RV32I-FPELIM-NEXT: addi a0, zero, 1
+; RV32I-FPELIM-NEXT: sw a0, 24(sp)
+; RV32I-FPELIM-NEXT: lui a0, 524272
+; RV32I-FPELIM-NEXT: mv a0, a0
+; RV32I-FPELIM-NEXT: sw a0, 12(sp)
+; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_scalars)
+; RV32I-FPELIM-NEXT: addi a2, a0, %lo(callee_large_scalars)
+; RV32I-FPELIM-NEXT: addi a0, sp, 24
+; RV32I-FPELIM-NEXT: mv a1, sp
+; RV32I-FPELIM-NEXT: jalr a2
+; RV32I-FPELIM-NEXT: lw ra, 44(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 48
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: caller_large_scalars:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -48
+; RV32I-WITHFP-NEXT: sw ra, 44(sp)
+; RV32I-WITHFP-NEXT: sw s0, 40(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 48
+; RV32I-WITHFP-NEXT: sw zero, -40(s0)
+; RV32I-WITHFP-NEXT: sw zero, -44(s0)
+; RV32I-WITHFP-NEXT: sw zero, -48(s0)
+; RV32I-WITHFP-NEXT: sw zero, -12(s0)
+; RV32I-WITHFP-NEXT: sw zero, -16(s0)
+; RV32I-WITHFP-NEXT: sw zero, -20(s0)
+; RV32I-WITHFP-NEXT: addi a0, zero, 1
+; RV32I-WITHFP-NEXT: sw a0, -24(s0)
+; RV32I-WITHFP-NEXT: lui a0, 524272
+; RV32I-WITHFP-NEXT: mv a0, a0
+; RV32I-WITHFP-NEXT: sw a0, -36(s0)
+; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_scalars)
+; RV32I-WITHFP-NEXT: addi a2, a0, %lo(callee_large_scalars)
+; RV32I-WITHFP-NEXT: addi a0, s0, -24
+; RV32I-WITHFP-NEXT: addi a1, s0, -48
+; RV32I-WITHFP-NEXT: jalr a2
+; RV32I-WITHFP-NEXT: lw s0, 40(sp)
+; RV32I-WITHFP-NEXT: lw ra, 44(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 48
+; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_large_scalars(i128 1, fp128 0xL00000000000000007FFF000000000000)
ret i32 %1
}
@@ -146,34 +241,56 @@ define i32 @caller_large_scalars() nounw
define i32 @callee_large_scalars_exhausted_regs(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i128 %h, i32 %i, fp128 %j) nounwind {
; Check that arguments larger than 2*xlen are handled correctly when their
; address is passed on the stack rather than in memory
-; RV32I-LABEL: callee_large_scalars_exhausted_regs:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lw a0, 4(s0)
-; RV32I-NEXT: lw a1, 12(a0)
-; RV32I-NEXT: lw a2, 12(a7)
-; RV32I-NEXT: xor a1, a2, a1
-; RV32I-NEXT: lw a2, 4(a0)
-; RV32I-NEXT: lw a3, 4(a7)
-; RV32I-NEXT: xor a2, a3, a2
-; RV32I-NEXT: or a1, a2, a1
-; RV32I-NEXT: lw a2, 8(a0)
-; RV32I-NEXT: lw a3, 8(a7)
-; RV32I-NEXT: xor a2, a3, a2
-; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: lw a3, 0(a7)
-; RV32I-NEXT: xor a0, a3, a0
-; RV32I-NEXT: or a0, a0, a2
-; RV32I-NEXT: or a0, a0, a1
-; RV32I-NEXT: xor a0, a0, zero
-; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: callee_large_scalars_exhausted_regs:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: lw a0, 4(sp)
+; RV32I-FPELIM-NEXT: lw a1, 12(a0)
+; RV32I-FPELIM-NEXT: lw a2, 12(a7)
+; RV32I-FPELIM-NEXT: xor a1, a2, a1
+; RV32I-FPELIM-NEXT: lw a2, 4(a0)
+; RV32I-FPELIM-NEXT: lw a3, 4(a7)
+; RV32I-FPELIM-NEXT: xor a2, a3, a2
+; RV32I-FPELIM-NEXT: or a1, a2, a1
+; RV32I-FPELIM-NEXT: lw a2, 8(a0)
+; RV32I-FPELIM-NEXT: lw a3, 8(a7)
+; RV32I-FPELIM-NEXT: xor a2, a3, a2
+; RV32I-FPELIM-NEXT: lw a0, 0(a0)
+; RV32I-FPELIM-NEXT: lw a3, 0(a7)
+; RV32I-FPELIM-NEXT: xor a0, a3, a0
+; RV32I-FPELIM-NEXT: or a0, a0, a2
+; RV32I-FPELIM-NEXT: or a0, a0, a1
+; RV32I-FPELIM-NEXT: xor a0, a0, zero
+; RV32I-FPELIM-NEXT: seqz a0, a0
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: callee_large_scalars_exhausted_regs:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -16
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: lw a0, 4(s0)
+; RV32I-WITHFP-NEXT: lw a1, 12(a0)
+; RV32I-WITHFP-NEXT: lw a2, 12(a7)
+; RV32I-WITHFP-NEXT: xor a1, a2, a1
+; RV32I-WITHFP-NEXT: lw a2, 4(a0)
+; RV32I-WITHFP-NEXT: lw a3, 4(a7)
+; RV32I-WITHFP-NEXT: xor a2, a3, a2
+; RV32I-WITHFP-NEXT: or a1, a2, a1
+; RV32I-WITHFP-NEXT: lw a2, 8(a0)
+; RV32I-WITHFP-NEXT: lw a3, 8(a7)
+; RV32I-WITHFP-NEXT: xor a2, a3, a2
+; RV32I-WITHFP-NEXT: lw a0, 0(a0)
+; RV32I-WITHFP-NEXT: lw a3, 0(a7)
+; RV32I-WITHFP-NEXT: xor a0, a3, a0
+; RV32I-WITHFP-NEXT: or a0, a0, a2
+; RV32I-WITHFP-NEXT: or a0, a0, a1
+; RV32I-WITHFP-NEXT: xor a0, a0, zero
+; RV32I-WITHFP-NEXT: seqz a0, a0
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 16
+; RV32I-WITHFP-NEXT: ret
%j_bitcast = bitcast fp128 %j to i128
%1 = icmp eq i128 %h, %j_bitcast
%2 = zext i1 %1 to i32
@@ -181,42 +298,76 @@ define i32 @callee_large_scalars_exhaust
}
define i32 @caller_large_scalars_exhausted_regs() nounwind {
-; RV32I-LABEL: caller_large_scalars_exhausted_regs:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -64
-; RV32I-NEXT: sw ra, 60(sp)
-; RV32I-NEXT: sw s0, 56(sp)
-; RV32I-NEXT: addi s0, sp, 64
-; RV32I-NEXT: addi a0, s0, -48
-; RV32I-NEXT: sw a0, 4(sp)
-; RV32I-NEXT: addi a0, zero, 9
-; RV32I-NEXT: sw a0, 0(sp)
-; RV32I-NEXT: sw zero, -40(s0)
-; RV32I-NEXT: sw zero, -44(s0)
-; RV32I-NEXT: sw zero, -48(s0)
-; RV32I-NEXT: sw zero, -12(s0)
-; RV32I-NEXT: sw zero, -16(s0)
-; RV32I-NEXT: sw zero, -20(s0)
-; RV32I-NEXT: addi a0, zero, 8
-; RV32I-NEXT: sw a0, -24(s0)
-; RV32I-NEXT: lui a0, 524272
-; RV32I-NEXT: mv a0, a0
-; RV32I-NEXT: sw a0, -36(s0)
-; RV32I-NEXT: lui a0, %hi(callee_large_scalars_exhausted_regs)
-; RV32I-NEXT: addi t0, a0, %lo(callee_large_scalars_exhausted_regs)
-; RV32I-NEXT: addi a0, zero, 1
-; RV32I-NEXT: addi a1, zero, 2
-; RV32I-NEXT: addi a2, zero, 3
-; RV32I-NEXT: addi a3, zero, 4
-; RV32I-NEXT: addi a4, zero, 5
-; RV32I-NEXT: addi a5, zero, 6
-; RV32I-NEXT: addi a6, zero, 7
-; RV32I-NEXT: addi a7, s0, -24
-; RV32I-NEXT: jalr t0
-; RV32I-NEXT: lw s0, 56(sp)
-; RV32I-NEXT: lw ra, 60(sp)
-; RV32I-NEXT: addi sp, sp, 64
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: caller_large_scalars_exhausted_regs:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -64
+; RV32I-FPELIM-NEXT: sw ra, 60(sp)
+; RV32I-FPELIM-NEXT: addi a0, sp, 16
+; RV32I-FPELIM-NEXT: sw a0, 4(sp)
+; RV32I-FPELIM-NEXT: addi a0, zero, 9
+; RV32I-FPELIM-NEXT: sw a0, 0(sp)
+; RV32I-FPELIM-NEXT: sw zero, 24(sp)
+; RV32I-FPELIM-NEXT: sw zero, 20(sp)
+; RV32I-FPELIM-NEXT: sw zero, 16(sp)
+; RV32I-FPELIM-NEXT: sw zero, 52(sp)
+; RV32I-FPELIM-NEXT: sw zero, 48(sp)
+; RV32I-FPELIM-NEXT: sw zero, 44(sp)
+; RV32I-FPELIM-NEXT: addi a0, zero, 8
+; RV32I-FPELIM-NEXT: sw a0, 40(sp)
+; RV32I-FPELIM-NEXT: lui a0, 524272
+; RV32I-FPELIM-NEXT: mv a0, a0
+; RV32I-FPELIM-NEXT: sw a0, 28(sp)
+; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_scalars_exhausted_regs)
+; RV32I-FPELIM-NEXT: addi t0, a0, %lo(callee_large_scalars_exhausted_regs)
+; RV32I-FPELIM-NEXT: addi a0, zero, 1
+; RV32I-FPELIM-NEXT: addi a1, zero, 2
+; RV32I-FPELIM-NEXT: addi a2, zero, 3
+; RV32I-FPELIM-NEXT: addi a3, zero, 4
+; RV32I-FPELIM-NEXT: addi a4, zero, 5
+; RV32I-FPELIM-NEXT: addi a5, zero, 6
+; RV32I-FPELIM-NEXT: addi a6, zero, 7
+; RV32I-FPELIM-NEXT: addi a7, sp, 40
+; RV32I-FPELIM-NEXT: jalr t0
+; RV32I-FPELIM-NEXT: lw ra, 60(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 64
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: caller_large_scalars_exhausted_regs:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -64
+; RV32I-WITHFP-NEXT: sw ra, 60(sp)
+; RV32I-WITHFP-NEXT: sw s0, 56(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 64
+; RV32I-WITHFP-NEXT: addi a0, s0, -48
+; RV32I-WITHFP-NEXT: sw a0, 4(sp)
+; RV32I-WITHFP-NEXT: addi a0, zero, 9
+; RV32I-WITHFP-NEXT: sw a0, 0(sp)
+; RV32I-WITHFP-NEXT: sw zero, -40(s0)
+; RV32I-WITHFP-NEXT: sw zero, -44(s0)
+; RV32I-WITHFP-NEXT: sw zero, -48(s0)
+; RV32I-WITHFP-NEXT: sw zero, -12(s0)
+; RV32I-WITHFP-NEXT: sw zero, -16(s0)
+; RV32I-WITHFP-NEXT: sw zero, -20(s0)
+; RV32I-WITHFP-NEXT: addi a0, zero, 8
+; RV32I-WITHFP-NEXT: sw a0, -24(s0)
+; RV32I-WITHFP-NEXT: lui a0, 524272
+; RV32I-WITHFP-NEXT: mv a0, a0
+; RV32I-WITHFP-NEXT: sw a0, -36(s0)
+; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_scalars_exhausted_regs)
+; RV32I-WITHFP-NEXT: addi t0, a0, %lo(callee_large_scalars_exhausted_regs)
+; RV32I-WITHFP-NEXT: addi a0, zero, 1
+; RV32I-WITHFP-NEXT: addi a1, zero, 2
+; RV32I-WITHFP-NEXT: addi a2, zero, 3
+; RV32I-WITHFP-NEXT: addi a3, zero, 4
+; RV32I-WITHFP-NEXT: addi a4, zero, 5
+; RV32I-WITHFP-NEXT: addi a5, zero, 6
+; RV32I-WITHFP-NEXT: addi a6, zero, 7
+; RV32I-WITHFP-NEXT: addi a7, s0, -24
+; RV32I-WITHFP-NEXT: jalr t0
+; RV32I-WITHFP-NEXT: lw s0, 56(sp)
+; RV32I-WITHFP-NEXT: lw ra, 60(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 64
+; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_large_scalars_exhausted_regs(
i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i128 8, i32 9,
fp128 0xL00000000000000007FFF000000000000)
@@ -226,23 +377,38 @@ define i32 @caller_large_scalars_exhaust
; Ensure that libcalls generated in the middle-end obey the calling convention
define i32 @caller_mixed_scalar_libcalls(i64 %a) nounwind {
-; RV32I-LABEL: caller_mixed_scalar_libcalls:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: addi s0, sp, 32
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: lui a0, %hi(__floatditf)
-; RV32I-NEXT: addi a3, a0, %lo(__floatditf)
-; RV32I-NEXT: addi a0, s0, -24
-; RV32I-NEXT: jalr a3
-; RV32I-NEXT: lw a0, -24(s0)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: caller_mixed_scalar_libcalls:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -32
+; RV32I-FPELIM-NEXT: sw ra, 28(sp)
+; RV32I-FPELIM-NEXT: mv a2, a1
+; RV32I-FPELIM-NEXT: mv a1, a0
+; RV32I-FPELIM-NEXT: lui a0, %hi(__floatditf)
+; RV32I-FPELIM-NEXT: addi a3, a0, %lo(__floatditf)
+; RV32I-FPELIM-NEXT: addi a0, sp, 8
+; RV32I-FPELIM-NEXT: jalr a3
+; RV32I-FPELIM-NEXT: lw a0, 8(sp)
+; RV32I-FPELIM-NEXT: lw ra, 28(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 32
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: caller_mixed_scalar_libcalls:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -32
+; RV32I-WITHFP-NEXT: sw ra, 28(sp)
+; RV32I-WITHFP-NEXT: sw s0, 24(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 32
+; RV32I-WITHFP-NEXT: mv a2, a1
+; RV32I-WITHFP-NEXT: mv a1, a0
+; RV32I-WITHFP-NEXT: lui a0, %hi(__floatditf)
+; RV32I-WITHFP-NEXT: addi a3, a0, %lo(__floatditf)
+; RV32I-WITHFP-NEXT: addi a0, s0, -24
+; RV32I-WITHFP-NEXT: jalr a3
+; RV32I-WITHFP-NEXT: lw a0, -24(s0)
+; RV32I-WITHFP-NEXT: lw s0, 24(sp)
+; RV32I-WITHFP-NEXT: lw ra, 28(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 32
+; RV32I-WITHFP-NEXT: ret
%1 = sitofp i64 %a to fp128
%2 = bitcast fp128 %1 to i128
%3 = trunc i128 %2 to i32
@@ -252,33 +418,54 @@ define i32 @caller_mixed_scalar_libcalls
; Check that the stack is used once the GPRs are exhausted
define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i64 %d, i32 %e, i32 %f, i64 %g, i32 %h) nounwind {
-; RV32I-LABEL: callee_many_scalars:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lw t0, 0(s0)
-; RV32I-NEXT: xor a4, a4, t0
-; RV32I-NEXT: xor a3, a3, a7
-; RV32I-NEXT: or a3, a3, a4
-; RV32I-NEXT: xor a3, a3, zero
-; RV32I-NEXT: lui a4, 16
-; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: and a1, a1, a4
-; RV32I-NEXT: andi a0, a0, 255
-; RV32I-NEXT: add a0, a0, a1
-; RV32I-NEXT: add a0, a0, a2
-; RV32I-NEXT: seqz a1, a3
-; RV32I-NEXT: add a0, a1, a0
-; RV32I-NEXT: add a0, a0, a5
-; RV32I-NEXT: add a0, a0, a6
-; RV32I-NEXT: lw a1, 4(s0)
-; RV32I-NEXT: add a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: callee_many_scalars:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: lw t0, 0(sp)
+; RV32I-FPELIM-NEXT: xor a4, a4, t0
+; RV32I-FPELIM-NEXT: xor a3, a3, a7
+; RV32I-FPELIM-NEXT: or a3, a3, a4
+; RV32I-FPELIM-NEXT: xor a3, a3, zero
+; RV32I-FPELIM-NEXT: lui a4, 16
+; RV32I-FPELIM-NEXT: addi a4, a4, -1
+; RV32I-FPELIM-NEXT: and a1, a1, a4
+; RV32I-FPELIM-NEXT: andi a0, a0, 255
+; RV32I-FPELIM-NEXT: add a0, a0, a1
+; RV32I-FPELIM-NEXT: add a0, a0, a2
+; RV32I-FPELIM-NEXT: seqz a1, a3
+; RV32I-FPELIM-NEXT: add a0, a1, a0
+; RV32I-FPELIM-NEXT: add a0, a0, a5
+; RV32I-FPELIM-NEXT: add a0, a0, a6
+; RV32I-FPELIM-NEXT: lw a1, 4(sp)
+; RV32I-FPELIM-NEXT: add a0, a0, a1
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: callee_many_scalars:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -16
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: lw t0, 0(s0)
+; RV32I-WITHFP-NEXT: xor a4, a4, t0
+; RV32I-WITHFP-NEXT: xor a3, a3, a7
+; RV32I-WITHFP-NEXT: or a3, a3, a4
+; RV32I-WITHFP-NEXT: xor a3, a3, zero
+; RV32I-WITHFP-NEXT: lui a4, 16
+; RV32I-WITHFP-NEXT: addi a4, a4, -1
+; RV32I-WITHFP-NEXT: and a1, a1, a4
+; RV32I-WITHFP-NEXT: andi a0, a0, 255
+; RV32I-WITHFP-NEXT: add a0, a0, a1
+; RV32I-WITHFP-NEXT: add a0, a0, a2
+; RV32I-WITHFP-NEXT: seqz a1, a3
+; RV32I-WITHFP-NEXT: add a0, a1, a0
+; RV32I-WITHFP-NEXT: add a0, a0, a5
+; RV32I-WITHFP-NEXT: add a0, a0, a6
+; RV32I-WITHFP-NEXT: lw a1, 4(s0)
+; RV32I-WITHFP-NEXT: add a0, a0, a1
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 16
+; RV32I-WITHFP-NEXT: ret
%a_ext = zext i8 %a to i32
%b_ext = zext i16 %b to i32
%1 = add i32 %a_ext, %b_ext
@@ -293,30 +480,52 @@ define i32 @callee_many_scalars(i8 %a, i
}
define i32 @caller_many_scalars() nounwind {
-; RV32I-LABEL: caller_many_scalars:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: addi s0, sp, 32
-; RV32I-NEXT: addi a0, zero, 8
-; RV32I-NEXT: sw a0, 4(sp)
-; RV32I-NEXT: sw zero, 0(sp)
-; RV32I-NEXT: lui a0, %hi(callee_many_scalars)
-; RV32I-NEXT: addi t0, a0, %lo(callee_many_scalars)
-; RV32I-NEXT: addi a0, zero, 1
-; RV32I-NEXT: addi a1, zero, 2
-; RV32I-NEXT: addi a2, zero, 3
-; RV32I-NEXT: addi a3, zero, 4
-; RV32I-NEXT: addi a5, zero, 5
-; RV32I-NEXT: addi a6, zero, 6
-; RV32I-NEXT: addi a7, zero, 7
-; RV32I-NEXT: mv a4, zero
-; RV32I-NEXT: jalr t0
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: caller_many_scalars:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -16
+; RV32I-FPELIM-NEXT: sw ra, 12(sp)
+; RV32I-FPELIM-NEXT: addi a0, zero, 8
+; RV32I-FPELIM-NEXT: sw a0, 4(sp)
+; RV32I-FPELIM-NEXT: sw zero, 0(sp)
+; RV32I-FPELIM-NEXT: lui a0, %hi(callee_many_scalars)
+; RV32I-FPELIM-NEXT: addi t0, a0, %lo(callee_many_scalars)
+; RV32I-FPELIM-NEXT: addi a0, zero, 1
+; RV32I-FPELIM-NEXT: addi a1, zero, 2
+; RV32I-FPELIM-NEXT: addi a2, zero, 3
+; RV32I-FPELIM-NEXT: addi a3, zero, 4
+; RV32I-FPELIM-NEXT: addi a5, zero, 5
+; RV32I-FPELIM-NEXT: addi a6, zero, 6
+; RV32I-FPELIM-NEXT: addi a7, zero, 7
+; RV32I-FPELIM-NEXT: mv a4, zero
+; RV32I-FPELIM-NEXT: jalr t0
+; RV32I-FPELIM-NEXT: lw ra, 12(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 16
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: caller_many_scalars:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -32
+; RV32I-WITHFP-NEXT: sw ra, 28(sp)
+; RV32I-WITHFP-NEXT: sw s0, 24(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 32
+; RV32I-WITHFP-NEXT: addi a0, zero, 8
+; RV32I-WITHFP-NEXT: sw a0, 4(sp)
+; RV32I-WITHFP-NEXT: sw zero, 0(sp)
+; RV32I-WITHFP-NEXT: lui a0, %hi(callee_many_scalars)
+; RV32I-WITHFP-NEXT: addi t0, a0, %lo(callee_many_scalars)
+; RV32I-WITHFP-NEXT: addi a0, zero, 1
+; RV32I-WITHFP-NEXT: addi a1, zero, 2
+; RV32I-WITHFP-NEXT: addi a2, zero, 3
+; RV32I-WITHFP-NEXT: addi a3, zero, 4
+; RV32I-WITHFP-NEXT: addi a5, zero, 5
+; RV32I-WITHFP-NEXT: addi a6, zero, 6
+; RV32I-WITHFP-NEXT: addi a7, zero, 7
+; RV32I-WITHFP-NEXT: mv a4, zero
+; RV32I-WITHFP-NEXT: jalr t0
+; RV32I-WITHFP-NEXT: lw s0, 24(sp)
+; RV32I-WITHFP-NEXT: lw ra, 28(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 32
+; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_many_scalars(i8 1, i16 2, i32 3, i64 4, i32 5, i32 6, i64 7, i32 8)
ret i32 %1
}
@@ -326,18 +535,24 @@ define i32 @caller_many_scalars() nounwi
%struct.small = type { i32, i32* }
define i32 @callee_small_coerced_struct([2 x i32] %a.coerce) nounwind {
-; RV32I-LABEL: callee_small_coerced_struct:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: callee_small_coerced_struct:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: xor a0, a0, a1
+; RV32I-FPELIM-NEXT: seqz a0, a0
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: callee_small_coerced_struct:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -16
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: xor a0, a0, a1
+; RV32I-WITHFP-NEXT: seqz a0, a0
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 16
+; RV32I-WITHFP-NEXT: ret
%1 = extractvalue [2 x i32] %a.coerce, 0
%2 = extractvalue [2 x i32] %a.coerce, 1
%3 = icmp eq i32 %1, %2
@@ -346,21 +561,34 @@ define i32 @callee_small_coerced_struct(
}
define i32 @caller_small_coerced_struct() nounwind {
-; RV32I-LABEL: caller_small_coerced_struct:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lui a0, %hi(callee_small_coerced_struct)
-; RV32I-NEXT: addi a2, a0, %lo(callee_small_coerced_struct)
-; RV32I-NEXT: addi a0, zero, 1
-; RV32I-NEXT: addi a1, zero, 2
-; RV32I-NEXT: jalr a2
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: caller_small_coerced_struct:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -16
+; RV32I-FPELIM-NEXT: sw ra, 12(sp)
+; RV32I-FPELIM-NEXT: lui a0, %hi(callee_small_coerced_struct)
+; RV32I-FPELIM-NEXT: addi a2, a0, %lo(callee_small_coerced_struct)
+; RV32I-FPELIM-NEXT: addi a0, zero, 1
+; RV32I-FPELIM-NEXT: addi a1, zero, 2
+; RV32I-FPELIM-NEXT: jalr a2
+; RV32I-FPELIM-NEXT: lw ra, 12(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 16
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: caller_small_coerced_struct:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -16
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: lui a0, %hi(callee_small_coerced_struct)
+; RV32I-WITHFP-NEXT: addi a2, a0, %lo(callee_small_coerced_struct)
+; RV32I-WITHFP-NEXT: addi a0, zero, 1
+; RV32I-WITHFP-NEXT: addi a1, zero, 2
+; RV32I-WITHFP-NEXT: jalr a2
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 16
+; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_small_coerced_struct([2 x i32] [i32 1, i32 2])
ret i32 %1
}
@@ -370,19 +598,26 @@ define i32 @caller_small_coerced_struct(
%struct.large = type { i32, i32, i32, i32 }
define i32 @callee_large_struct(%struct.large* byval align 4 %a) nounwind {
-; RV32I-LABEL: callee_large_struct:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lw a1, 12(a0)
-; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: add a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: callee_large_struct:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: lw a1, 12(a0)
+; RV32I-FPELIM-NEXT: lw a0, 0(a0)
+; RV32I-FPELIM-NEXT: add a0, a0, a1
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: callee_large_struct:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -16
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: lw a1, 12(a0)
+; RV32I-WITHFP-NEXT: lw a0, 0(a0)
+; RV32I-WITHFP-NEXT: add a0, a0, a1
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 16
+; RV32I-WITHFP-NEXT: ret
%1 = getelementptr inbounds %struct.large, %struct.large* %a, i32 0, i32 0
%2 = getelementptr inbounds %struct.large, %struct.large* %a, i32 0, i32 3
%3 = load i32, i32* %1
@@ -392,32 +627,56 @@ define i32 @callee_large_struct(%struct.
}
define i32 @caller_large_struct() nounwind {
-; RV32I-LABEL: caller_large_struct:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -48
-; RV32I-NEXT: sw ra, 44(sp)
-; RV32I-NEXT: sw s0, 40(sp)
-; RV32I-NEXT: addi s0, sp, 48
-; RV32I-NEXT: addi a0, zero, 1
-; RV32I-NEXT: sw a0, -24(s0)
-; RV32I-NEXT: sw a0, -40(s0)
-; RV32I-NEXT: addi a0, zero, 2
-; RV32I-NEXT: sw a0, -20(s0)
-; RV32I-NEXT: sw a0, -36(s0)
-; RV32I-NEXT: addi a0, zero, 3
-; RV32I-NEXT: sw a0, -16(s0)
-; RV32I-NEXT: sw a0, -32(s0)
-; RV32I-NEXT: addi a0, zero, 4
-; RV32I-NEXT: sw a0, -12(s0)
-; RV32I-NEXT: sw a0, -28(s0)
-; RV32I-NEXT: lui a0, %hi(callee_large_struct)
-; RV32I-NEXT: addi a1, a0, %lo(callee_large_struct)
-; RV32I-NEXT: addi a0, s0, -40
-; RV32I-NEXT: jalr a1
-; RV32I-NEXT: lw s0, 40(sp)
-; RV32I-NEXT: lw ra, 44(sp)
-; RV32I-NEXT: addi sp, sp, 48
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: caller_large_struct:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -48
+; RV32I-FPELIM-NEXT: sw ra, 44(sp)
+; RV32I-FPELIM-NEXT: addi a0, zero, 1
+; RV32I-FPELIM-NEXT: sw a0, 24(sp)
+; RV32I-FPELIM-NEXT: sw a0, 8(sp)
+; RV32I-FPELIM-NEXT: addi a0, zero, 2
+; RV32I-FPELIM-NEXT: sw a0, 28(sp)
+; RV32I-FPELIM-NEXT: sw a0, 12(sp)
+; RV32I-FPELIM-NEXT: addi a0, zero, 3
+; RV32I-FPELIM-NEXT: sw a0, 32(sp)
+; RV32I-FPELIM-NEXT: sw a0, 16(sp)
+; RV32I-FPELIM-NEXT: addi a0, zero, 4
+; RV32I-FPELIM-NEXT: sw a0, 36(sp)
+; RV32I-FPELIM-NEXT: sw a0, 20(sp)
+; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_struct)
+; RV32I-FPELIM-NEXT: addi a1, a0, %lo(callee_large_struct)
+; RV32I-FPELIM-NEXT: addi a0, sp, 8
+; RV32I-FPELIM-NEXT: jalr a1
+; RV32I-FPELIM-NEXT: lw ra, 44(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 48
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: caller_large_struct:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -48
+; RV32I-WITHFP-NEXT: sw ra, 44(sp)
+; RV32I-WITHFP-NEXT: sw s0, 40(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 48
+; RV32I-WITHFP-NEXT: addi a0, zero, 1
+; RV32I-WITHFP-NEXT: sw a0, -24(s0)
+; RV32I-WITHFP-NEXT: sw a0, -40(s0)
+; RV32I-WITHFP-NEXT: addi a0, zero, 2
+; RV32I-WITHFP-NEXT: sw a0, -20(s0)
+; RV32I-WITHFP-NEXT: sw a0, -36(s0)
+; RV32I-WITHFP-NEXT: addi a0, zero, 3
+; RV32I-WITHFP-NEXT: sw a0, -16(s0)
+; RV32I-WITHFP-NEXT: sw a0, -32(s0)
+; RV32I-WITHFP-NEXT: addi a0, zero, 4
+; RV32I-WITHFP-NEXT: sw a0, -12(s0)
+; RV32I-WITHFP-NEXT: sw a0, -28(s0)
+; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_struct)
+; RV32I-WITHFP-NEXT: addi a1, a0, %lo(callee_large_struct)
+; RV32I-WITHFP-NEXT: addi a0, s0, -40
+; RV32I-WITHFP-NEXT: jalr a1
+; RV32I-WITHFP-NEXT: lw s0, 40(sp)
+; RV32I-WITHFP-NEXT: lw ra, 44(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 48
+; RV32I-WITHFP-NEXT: ret
%ls = alloca %struct.large, align 4
%1 = bitcast %struct.large* %ls to i8*
%a = getelementptr inbounds %struct.large, %struct.large* %ls, i32 0, i32 0
@@ -437,26 +696,40 @@ define i32 @caller_large_struct() nounwi
define i32 @callee_aligned_stack(i32 %a, i32 %b, fp128 %c, i32 %d, i32 %e, i64 %f, i32 %g, i32 %h, double %i, i32 %j, [2 x i32] %k) nounwind {
; The double should be 8-byte aligned on the stack, but the two-element array
; should only be 4-byte aligned
-; RV32I-LABEL: callee_aligned_stack:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lw a0, 0(a2)
-; RV32I-NEXT: add a0, a0, a7
-; RV32I-NEXT: lw a1, 0(s0)
-; RV32I-NEXT: add a0, a0, a1
-; RV32I-NEXT: lw a1, 8(s0)
-; RV32I-NEXT: add a0, a0, a1
-; RV32I-NEXT: lw a1, 16(s0)
-; RV32I-NEXT: add a0, a0, a1
-; RV32I-NEXT: lw a1, 20(s0)
-; RV32I-NEXT: add a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: callee_aligned_stack:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: lw a0, 0(a2)
+; RV32I-FPELIM-NEXT: add a0, a0, a7
+; RV32I-FPELIM-NEXT: lw a1, 0(sp)
+; RV32I-FPELIM-NEXT: add a0, a0, a1
+; RV32I-FPELIM-NEXT: lw a1, 8(sp)
+; RV32I-FPELIM-NEXT: add a0, a0, a1
+; RV32I-FPELIM-NEXT: lw a1, 16(sp)
+; RV32I-FPELIM-NEXT: add a0, a0, a1
+; RV32I-FPELIM-NEXT: lw a1, 20(sp)
+; RV32I-FPELIM-NEXT: add a0, a0, a1
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: callee_aligned_stack:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -16
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: lw a0, 0(a2)
+; RV32I-WITHFP-NEXT: add a0, a0, a7
+; RV32I-WITHFP-NEXT: lw a1, 0(s0)
+; RV32I-WITHFP-NEXT: add a0, a0, a1
+; RV32I-WITHFP-NEXT: lw a1, 8(s0)
+; RV32I-WITHFP-NEXT: add a0, a0, a1
+; RV32I-WITHFP-NEXT: lw a1, 16(s0)
+; RV32I-WITHFP-NEXT: add a0, a0, a1
+; RV32I-WITHFP-NEXT: lw a1, 20(s0)
+; RV32I-WITHFP-NEXT: add a0, a0, a1
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 16
+; RV32I-WITHFP-NEXT: ret
%1 = bitcast fp128 %c to i128
%2 = trunc i128 %1 to i32
%3 = add i32 %2, %g
@@ -473,54 +746,100 @@ define i32 @callee_aligned_stack(i32 %a,
define void @caller_aligned_stack() nounwind {
; The double should be 8-byte aligned on the stack, but the two-element array
; should only be 4-byte aligned
-; RV32I-LABEL: caller_aligned_stack:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -64
-; RV32I-NEXT: sw ra, 60(sp)
-; RV32I-NEXT: sw s0, 56(sp)
-; RV32I-NEXT: addi s0, sp, 64
-; RV32I-NEXT: addi a0, zero, 18
-; RV32I-NEXT: sw a0, 24(sp)
-; RV32I-NEXT: addi a0, zero, 17
-; RV32I-NEXT: sw a0, 20(sp)
-; RV32I-NEXT: addi a0, zero, 16
-; RV32I-NEXT: sw a0, 16(sp)
-; RV32I-NEXT: lui a0, 262236
-; RV32I-NEXT: addi a0, a0, 655
-; RV32I-NEXT: sw a0, 12(sp)
-; RV32I-NEXT: lui a0, 377487
-; RV32I-NEXT: addi a0, a0, 1475
-; RV32I-NEXT: sw a0, 8(sp)
-; RV32I-NEXT: addi a0, zero, 15
-; RV32I-NEXT: sw a0, 0(sp)
-; RV32I-NEXT: lui a0, 262153
-; RV32I-NEXT: addi a0, a0, 491
-; RV32I-NEXT: sw a0, -20(s0)
-; RV32I-NEXT: lui a0, 545260
-; RV32I-NEXT: addi a0, a0, -1967
-; RV32I-NEXT: sw a0, -24(s0)
-; RV32I-NEXT: lui a0, 964690
-; RV32I-NEXT: addi a0, a0, -328
-; RV32I-NEXT: sw a0, -28(s0)
-; RV32I-NEXT: lui a0, 335544
-; RV32I-NEXT: addi a0, a0, 1311
-; RV32I-NEXT: sw a0, -32(s0)
-; RV32I-NEXT: lui a0, 688509
-; RV32I-NEXT: addi a5, a0, -2048
-; RV32I-NEXT: lui a0, %hi(callee_aligned_stack)
-; RV32I-NEXT: addi t0, a0, %lo(callee_aligned_stack)
-; RV32I-NEXT: addi a0, zero, 1
-; RV32I-NEXT: addi a1, zero, 11
-; RV32I-NEXT: addi a2, s0, -32
-; RV32I-NEXT: addi a3, zero, 12
-; RV32I-NEXT: addi a4, zero, 13
-; RV32I-NEXT: addi a6, zero, 4
-; RV32I-NEXT: addi a7, zero, 14
-; RV32I-NEXT: jalr t0
-; RV32I-NEXT: lw s0, 56(sp)
-; RV32I-NEXT: lw ra, 60(sp)
-; RV32I-NEXT: addi sp, sp, 64
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: caller_aligned_stack:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -64
+; RV32I-FPELIM-NEXT: sw ra, 60(sp)
+; RV32I-FPELIM-NEXT: addi a0, zero, 18
+; RV32I-FPELIM-NEXT: sw a0, 24(sp)
+; RV32I-FPELIM-NEXT: addi a0, zero, 17
+; RV32I-FPELIM-NEXT: sw a0, 20(sp)
+; RV32I-FPELIM-NEXT: addi a0, zero, 16
+; RV32I-FPELIM-NEXT: sw a0, 16(sp)
+; RV32I-FPELIM-NEXT: lui a0, 262236
+; RV32I-FPELIM-NEXT: addi a0, a0, 655
+; RV32I-FPELIM-NEXT: sw a0, 12(sp)
+; RV32I-FPELIM-NEXT: lui a0, 377487
+; RV32I-FPELIM-NEXT: addi a0, a0, 1475
+; RV32I-FPELIM-NEXT: sw a0, 8(sp)
+; RV32I-FPELIM-NEXT: addi a0, zero, 15
+; RV32I-FPELIM-NEXT: sw a0, 0(sp)
+; RV32I-FPELIM-NEXT: lui a0, 262153
+; RV32I-FPELIM-NEXT: addi a0, a0, 491
+; RV32I-FPELIM-NEXT: sw a0, 44(sp)
+; RV32I-FPELIM-NEXT: lui a0, 545260
+; RV32I-FPELIM-NEXT: addi a0, a0, -1967
+; RV32I-FPELIM-NEXT: sw a0, 40(sp)
+; RV32I-FPELIM-NEXT: lui a0, 964690
+; RV32I-FPELIM-NEXT: addi a0, a0, -328
+; RV32I-FPELIM-NEXT: sw a0, 36(sp)
+; RV32I-FPELIM-NEXT: lui a0, 335544
+; RV32I-FPELIM-NEXT: addi a0, a0, 1311
+; RV32I-FPELIM-NEXT: sw a0, 32(sp)
+; RV32I-FPELIM-NEXT: lui a0, 688509
+; RV32I-FPELIM-NEXT: addi a5, a0, -2048
+; RV32I-FPELIM-NEXT: lui a0, %hi(callee_aligned_stack)
+; RV32I-FPELIM-NEXT: addi t0, a0, %lo(callee_aligned_stack)
+; RV32I-FPELIM-NEXT: addi a0, zero, 1
+; RV32I-FPELIM-NEXT: addi a1, zero, 11
+; RV32I-FPELIM-NEXT: addi a2, sp, 32
+; RV32I-FPELIM-NEXT: addi a3, zero, 12
+; RV32I-FPELIM-NEXT: addi a4, zero, 13
+; RV32I-FPELIM-NEXT: addi a6, zero, 4
+; RV32I-FPELIM-NEXT: addi a7, zero, 14
+; RV32I-FPELIM-NEXT: jalr t0
+; RV32I-FPELIM-NEXT: lw ra, 60(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 64
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: caller_aligned_stack:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -64
+; RV32I-WITHFP-NEXT: sw ra, 60(sp)
+; RV32I-WITHFP-NEXT: sw s0, 56(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 64
+; RV32I-WITHFP-NEXT: addi a0, zero, 18
+; RV32I-WITHFP-NEXT: sw a0, 24(sp)
+; RV32I-WITHFP-NEXT: addi a0, zero, 17
+; RV32I-WITHFP-NEXT: sw a0, 20(sp)
+; RV32I-WITHFP-NEXT: addi a0, zero, 16
+; RV32I-WITHFP-NEXT: sw a0, 16(sp)
+; RV32I-WITHFP-NEXT: lui a0, 262236
+; RV32I-WITHFP-NEXT: addi a0, a0, 655
+; RV32I-WITHFP-NEXT: sw a0, 12(sp)
+; RV32I-WITHFP-NEXT: lui a0, 377487
+; RV32I-WITHFP-NEXT: addi a0, a0, 1475
+; RV32I-WITHFP-NEXT: sw a0, 8(sp)
+; RV32I-WITHFP-NEXT: addi a0, zero, 15
+; RV32I-WITHFP-NEXT: sw a0, 0(sp)
+; RV32I-WITHFP-NEXT: lui a0, 262153
+; RV32I-WITHFP-NEXT: addi a0, a0, 491
+; RV32I-WITHFP-NEXT: sw a0, -20(s0)
+; RV32I-WITHFP-NEXT: lui a0, 545260
+; RV32I-WITHFP-NEXT: addi a0, a0, -1967
+; RV32I-WITHFP-NEXT: sw a0, -24(s0)
+; RV32I-WITHFP-NEXT: lui a0, 964690
+; RV32I-WITHFP-NEXT: addi a0, a0, -328
+; RV32I-WITHFP-NEXT: sw a0, -28(s0)
+; RV32I-WITHFP-NEXT: lui a0, 335544
+; RV32I-WITHFP-NEXT: addi a0, a0, 1311
+; RV32I-WITHFP-NEXT: sw a0, -32(s0)
+; RV32I-WITHFP-NEXT: lui a0, 688509
+; RV32I-WITHFP-NEXT: addi a5, a0, -2048
+; RV32I-WITHFP-NEXT: lui a0, %hi(callee_aligned_stack)
+; RV32I-WITHFP-NEXT: addi t0, a0, %lo(callee_aligned_stack)
+; RV32I-WITHFP-NEXT: addi a0, zero, 1
+; RV32I-WITHFP-NEXT: addi a1, zero, 11
+; RV32I-WITHFP-NEXT: addi a2, s0, -32
+; RV32I-WITHFP-NEXT: addi a3, zero, 12
+; RV32I-WITHFP-NEXT: addi a4, zero, 13
+; RV32I-WITHFP-NEXT: addi a6, zero, 4
+; RV32I-WITHFP-NEXT: addi a7, zero, 14
+; RV32I-WITHFP-NEXT: jalr t0
+; RV32I-WITHFP-NEXT: lw s0, 56(sp)
+; RV32I-WITHFP-NEXT: lw ra, 60(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 64
+; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_aligned_stack(i32 1, i32 11,
fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13,
i64 20000000000, i32 14, i32 15, double 2.720000e+00, i32 16,
@@ -531,45 +850,72 @@ define void @caller_aligned_stack() noun
; Check return of 2x xlen scalars
define i64 @callee_small_scalar_ret() nounwind {
-; RV32I-LABEL: callee_small_scalar_ret:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lui a0, 466866
-; RV32I-NEXT: addi a0, a0, 1677
-; RV32I-NEXT: addi a1, zero, 287
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: callee_small_scalar_ret:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: lui a0, 466866
+; RV32I-FPELIM-NEXT: addi a0, a0, 1677
+; RV32I-FPELIM-NEXT: addi a1, zero, 287
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: callee_small_scalar_ret:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -16
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: lui a0, 466866
+; RV32I-WITHFP-NEXT: addi a0, a0, 1677
+; RV32I-WITHFP-NEXT: addi a1, zero, 287
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 16
+; RV32I-WITHFP-NEXT: ret
ret i64 1234567898765
}
define i32 @caller_small_scalar_ret() nounwind {
-; RV32I-LABEL: caller_small_scalar_ret:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lui a0, %hi(callee_small_scalar_ret)
-; RV32I-NEXT: addi a0, a0, %lo(callee_small_scalar_ret)
-; RV32I-NEXT: jalr a0
-; RV32I-NEXT: lui a2, 56
-; RV32I-NEXT: addi a2, a2, 580
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: lui a2, 200614
-; RV32I-NEXT: addi a2, a2, 647
-; RV32I-NEXT: xor a0, a0, a2
-; RV32I-NEXT: or a0, a0, a1
-; RV32I-NEXT: xor a0, a0, zero
-; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: caller_small_scalar_ret:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -16
+; RV32I-FPELIM-NEXT: sw ra, 12(sp)
+; RV32I-FPELIM-NEXT: lui a0, %hi(callee_small_scalar_ret)
+; RV32I-FPELIM-NEXT: addi a0, a0, %lo(callee_small_scalar_ret)
+; RV32I-FPELIM-NEXT: jalr a0
+; RV32I-FPELIM-NEXT: lui a2, 56
+; RV32I-FPELIM-NEXT: addi a2, a2, 580
+; RV32I-FPELIM-NEXT: xor a1, a1, a2
+; RV32I-FPELIM-NEXT: lui a2, 200614
+; RV32I-FPELIM-NEXT: addi a2, a2, 647
+; RV32I-FPELIM-NEXT: xor a0, a0, a2
+; RV32I-FPELIM-NEXT: or a0, a0, a1
+; RV32I-FPELIM-NEXT: xor a0, a0, zero
+; RV32I-FPELIM-NEXT: seqz a0, a0
+; RV32I-FPELIM-NEXT: lw ra, 12(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 16
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: caller_small_scalar_ret:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -16
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: lui a0, %hi(callee_small_scalar_ret)
+; RV32I-WITHFP-NEXT: addi a0, a0, %lo(callee_small_scalar_ret)
+; RV32I-WITHFP-NEXT: jalr a0
+; RV32I-WITHFP-NEXT: lui a2, 56
+; RV32I-WITHFP-NEXT: addi a2, a2, 580
+; RV32I-WITHFP-NEXT: xor a1, a1, a2
+; RV32I-WITHFP-NEXT: lui a2, 200614
+; RV32I-WITHFP-NEXT: addi a2, a2, 647
+; RV32I-WITHFP-NEXT: xor a0, a0, a2
+; RV32I-WITHFP-NEXT: or a0, a0, a1
+; RV32I-WITHFP-NEXT: xor a0, a0, zero
+; RV32I-WITHFP-NEXT: seqz a0, a0
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 16
+; RV32I-WITHFP-NEXT: ret
%1 = call i64 @callee_small_scalar_ret()
%2 = icmp eq i64 987654321234567, %1
%3 = zext i1 %2 to i32
@@ -579,36 +925,54 @@ define i32 @caller_small_scalar_ret() no
; Check return of 2x xlen structs
define %struct.small @callee_small_struct_ret() nounwind {
-; RV32I-LABEL: callee_small_struct_ret:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: addi a0, zero, 1
-; RV32I-NEXT: mv a1, zero
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: callee_small_struct_ret:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi a0, zero, 1
+; RV32I-FPELIM-NEXT: mv a1, zero
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: callee_small_struct_ret:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -16
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: addi a0, zero, 1
+; RV32I-WITHFP-NEXT: mv a1, zero
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 16
+; RV32I-WITHFP-NEXT: ret
ret %struct.small { i32 1, i32* null }
}
define i32 @caller_small_struct_ret() nounwind {
-; RV32I-LABEL: caller_small_struct_ret:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lui a0, %hi(callee_small_struct_ret)
-; RV32I-NEXT: addi a0, a0, %lo(callee_small_struct_ret)
-; RV32I-NEXT: jalr a0
-; RV32I-NEXT: add a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: caller_small_struct_ret:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -16
+; RV32I-FPELIM-NEXT: sw ra, 12(sp)
+; RV32I-FPELIM-NEXT: lui a0, %hi(callee_small_struct_ret)
+; RV32I-FPELIM-NEXT: addi a0, a0, %lo(callee_small_struct_ret)
+; RV32I-FPELIM-NEXT: jalr a0
+; RV32I-FPELIM-NEXT: add a0, a0, a1
+; RV32I-FPELIM-NEXT: lw ra, 12(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 16
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: caller_small_struct_ret:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -16
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: lui a0, %hi(callee_small_struct_ret)
+; RV32I-WITHFP-NEXT: addi a0, a0, %lo(callee_small_struct_ret)
+; RV32I-WITHFP-NEXT: jalr a0
+; RV32I-WITHFP-NEXT: add a0, a0, a1
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 16
+; RV32I-WITHFP-NEXT: ret
%1 = call %struct.small @callee_small_struct_ret()
%2 = extractvalue %struct.small %1, 0
%3 = extractvalue %struct.small %1, 1
@@ -620,40 +984,62 @@ define i32 @caller_small_struct_ret() no
; Check return of >2x xlen scalars
define fp128 @callee_large_scalar_ret() nounwind {
-; RV32I-LABEL: callee_large_scalar_ret:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lui a1, 524272
-; RV32I-NEXT: mv a1, a1
-; RV32I-NEXT: sw a1, 12(a0)
-; RV32I-NEXT: sw zero, 8(a0)
-; RV32I-NEXT: sw zero, 4(a0)
-; RV32I-NEXT: sw zero, 0(a0)
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: callee_large_scalar_ret:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: lui a1, 524272
+; RV32I-FPELIM-NEXT: mv a1, a1
+; RV32I-FPELIM-NEXT: sw a1, 12(a0)
+; RV32I-FPELIM-NEXT: sw zero, 8(a0)
+; RV32I-FPELIM-NEXT: sw zero, 4(a0)
+; RV32I-FPELIM-NEXT: sw zero, 0(a0)
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: callee_large_scalar_ret:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -16
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: lui a1, 524272
+; RV32I-WITHFP-NEXT: mv a1, a1
+; RV32I-WITHFP-NEXT: sw a1, 12(a0)
+; RV32I-WITHFP-NEXT: sw zero, 8(a0)
+; RV32I-WITHFP-NEXT: sw zero, 4(a0)
+; RV32I-WITHFP-NEXT: sw zero, 0(a0)
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 16
+; RV32I-WITHFP-NEXT: ret
ret fp128 0xL00000000000000007FFF000000000000
}
define void @caller_large_scalar_ret() nounwind {
-; RV32I-LABEL: caller_large_scalar_ret:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: addi s0, sp, 32
-; RV32I-NEXT: lui a0, %hi(callee_large_scalar_ret)
-; RV32I-NEXT: addi a1, a0, %lo(callee_large_scalar_ret)
-; RV32I-NEXT: addi a0, s0, -32
-; RV32I-NEXT: jalr a1
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: caller_large_scalar_ret:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -32
+; RV32I-FPELIM-NEXT: sw ra, 28(sp)
+; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_scalar_ret)
+; RV32I-FPELIM-NEXT: addi a1, a0, %lo(callee_large_scalar_ret)
+; RV32I-FPELIM-NEXT: mv a0, sp
+; RV32I-FPELIM-NEXT: jalr a1
+; RV32I-FPELIM-NEXT: lw ra, 28(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 32
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: caller_large_scalar_ret:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -32
+; RV32I-WITHFP-NEXT: sw ra, 28(sp)
+; RV32I-WITHFP-NEXT: sw s0, 24(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 32
+; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_scalar_ret)
+; RV32I-WITHFP-NEXT: addi a1, a0, %lo(callee_large_scalar_ret)
+; RV32I-WITHFP-NEXT: addi a0, s0, -32
+; RV32I-WITHFP-NEXT: jalr a1
+; RV32I-WITHFP-NEXT: lw s0, 24(sp)
+; RV32I-WITHFP-NEXT: lw ra, 28(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 32
+; RV32I-WITHFP-NEXT: ret
%1 = call fp128 @callee_large_scalar_ret()
ret void
}
@@ -661,24 +1047,36 @@ define void @caller_large_scalar_ret() n
; Check return of >2x xlen structs
define void @callee_large_struct_ret(%struct.large* noalias sret %agg.result) nounwind {
-; RV32I-LABEL: callee_large_struct_ret:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: addi a1, zero, 2
-; RV32I-NEXT: sw a1, 4(a0)
-; RV32I-NEXT: addi a1, zero, 1
-; RV32I-NEXT: sw a1, 0(a0)
-; RV32I-NEXT: addi a1, zero, 3
-; RV32I-NEXT: sw a1, 8(a0)
-; RV32I-NEXT: addi a1, zero, 4
-; RV32I-NEXT: sw a1, 12(a0)
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: callee_large_struct_ret:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi a1, zero, 2
+; RV32I-FPELIM-NEXT: sw a1, 4(a0)
+; RV32I-FPELIM-NEXT: addi a1, zero, 1
+; RV32I-FPELIM-NEXT: sw a1, 0(a0)
+; RV32I-FPELIM-NEXT: addi a1, zero, 3
+; RV32I-FPELIM-NEXT: sw a1, 8(a0)
+; RV32I-FPELIM-NEXT: addi a1, zero, 4
+; RV32I-FPELIM-NEXT: sw a1, 12(a0)
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: callee_large_struct_ret:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -16
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: addi a1, zero, 2
+; RV32I-WITHFP-NEXT: sw a1, 4(a0)
+; RV32I-WITHFP-NEXT: addi a1, zero, 1
+; RV32I-WITHFP-NEXT: sw a1, 0(a0)
+; RV32I-WITHFP-NEXT: addi a1, zero, 3
+; RV32I-WITHFP-NEXT: sw a1, 8(a0)
+; RV32I-WITHFP-NEXT: addi a1, zero, 4
+; RV32I-WITHFP-NEXT: sw a1, 12(a0)
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 16
+; RV32I-WITHFP-NEXT: ret
%a = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 0
store i32 1, i32* %a, align 4
%b = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 1
@@ -691,23 +1089,38 @@ define void @callee_large_struct_ret(%st
}
define i32 @caller_large_struct_ret() nounwind {
-; RV32I-LABEL: caller_large_struct_ret:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: addi s0, sp, 32
-; RV32I-NEXT: lui a0, %hi(callee_large_struct_ret)
-; RV32I-NEXT: addi a1, a0, %lo(callee_large_struct_ret)
-; RV32I-NEXT: addi a0, s0, -24
-; RV32I-NEXT: jalr a1
-; RV32I-NEXT: lw a0, -12(s0)
-; RV32I-NEXT: lw a1, -24(s0)
-; RV32I-NEXT: add a0, a1, a0
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: caller_large_struct_ret:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -32
+; RV32I-FPELIM-NEXT: sw ra, 28(sp)
+; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_struct_ret)
+; RV32I-FPELIM-NEXT: addi a1, a0, %lo(callee_large_struct_ret)
+; RV32I-FPELIM-NEXT: addi a0, sp, 8
+; RV32I-FPELIM-NEXT: jalr a1
+; RV32I-FPELIM-NEXT: lw a0, 20(sp)
+; RV32I-FPELIM-NEXT: lw a1, 8(sp)
+; RV32I-FPELIM-NEXT: add a0, a1, a0
+; RV32I-FPELIM-NEXT: lw ra, 28(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 32
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: caller_large_struct_ret:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -32
+; RV32I-WITHFP-NEXT: sw ra, 28(sp)
+; RV32I-WITHFP-NEXT: sw s0, 24(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 32
+; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_struct_ret)
+; RV32I-WITHFP-NEXT: addi a1, a0, %lo(callee_large_struct_ret)
+; RV32I-WITHFP-NEXT: addi a0, s0, -24
+; RV32I-WITHFP-NEXT: jalr a1
+; RV32I-WITHFP-NEXT: lw a0, -12(s0)
+; RV32I-WITHFP-NEXT: lw a1, -24(s0)
+; RV32I-WITHFP-NEXT: add a0, a1, a0
+; RV32I-WITHFP-NEXT: lw s0, 24(sp)
+; RV32I-WITHFP-NEXT: lw ra, 28(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 32
+; RV32I-WITHFP-NEXT: ret
%1 = alloca %struct.large
call void @callee_large_struct_ret(%struct.large* sret %1)
%2 = getelementptr inbounds %struct.large, %struct.large* %1, i32 0, i32 0
Modified: llvm/trunk/test/CodeGen/RISCV/calls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/calls.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/calls.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/calls.ll Thu Jan 18 03:34:02 2018
@@ -9,12 +9,9 @@ define i32 @test_call_external(i32 %a) n
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(external_function)
; RV32I-NEXT: addi a1, a1, %lo(external_function)
; RV32I-NEXT: jalr a1
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -25,14 +22,7 @@ define i32 @test_call_external(i32 %a) n
define i32 @defined_function(i32 %a) nounwind {
; RV32I-LABEL: defined_function:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a0, a0, 1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = add i32 %a, 1
ret i32 %1
@@ -43,12 +33,9 @@ define i32 @test_call_defined(i32 %a) no
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(defined_function)
; RV32I-NEXT: addi a1, a1, %lo(defined_function)
; RV32I-NEXT: jalr a1
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -61,12 +48,9 @@ define i32 @test_call_indirect(i32 (i32)
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: jalr a2
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -80,14 +64,7 @@ define i32 @test_call_indirect(i32 (i32)
define fastcc i32 @fastcc_function(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: fastcc_function:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: add a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
@@ -98,17 +75,14 @@ define i32 @test_call_fastcc(i32 %a, i32
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: sw s1, 4(sp)
-; RV32I-NEXT: addi s0, sp, 16
+; RV32I-NEXT: sw s1, 8(sp)
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a0, %hi(fastcc_function)
; RV32I-NEXT: addi a2, a0, %lo(fastcc_function)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: jalr a2
; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: lw s1, 4(sp)
-; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw s1, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -121,11 +95,9 @@ declare i32 @external_many_args(i32, i32
define i32 @test_call_external_many_args(i32 %a) nounwind {
; RV32I-LABEL: test_call_external_many_args:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: addi s0, sp, 32
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s1, 8(sp)
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: sw s1, 0(sp)
@@ -141,10 +113,9 @@ define i32 @test_call_external_many_args
; RV32I-NEXT: mv a7, s1
; RV32I-NEXT: jalr t0
; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw s1, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = call i32 @external_many_args(i32 %a, i32 %a, i32 %a, i32 %a, i32 %a,
i32 %a, i32 %a, i32 %a, i32 %a, i32 %a)
@@ -154,15 +125,8 @@ define i32 @test_call_external_many_args
define i32 @defined_many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 %j) nounwind {
; RV32I-LABEL: defined_many_args:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lw a0, 4(s0)
+; RV32I-NEXT: lw a0, 4(sp)
; RV32I-NEXT: addi a0, a0, 1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%added = add i32 %j, 1
ret i32 %added
@@ -171,10 +135,8 @@ define i32 @defined_many_args(i32, i32,
define i32 @test_call_defined_many_args(i32 %a) nounwind {
; RV32I-LABEL: test_call_defined_many_args:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: addi s0, sp, 32
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw a0, 4(sp)
; RV32I-NEXT: sw a0, 0(sp)
; RV32I-NEXT: lui a1, %hi(defined_many_args)
@@ -187,9 +149,8 @@ define i32 @test_call_defined_many_args(
; RV32I-NEXT: mv a6, a0
; RV32I-NEXT: mv a7, a0
; RV32I-NEXT: jalr t0
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = call i32 @defined_many_args(i32 %a, i32 %a, i32 %a, i32 %a, i32 %a,
i32 %a, i32 %a, i32 %a, i32 %a, i32 %a)
Modified: llvm/trunk/test/CodeGen/RISCV/div.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/div.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/div.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/div.ll Thu Jan 18 03:34:02 2018
@@ -7,12 +7,9 @@ define i32 @udiv(i32 %a, i32 %b) nounwin
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a2, %hi(__udivsi3)
; RV32I-NEXT: addi a2, a2, %lo(__udivsi3)
; RV32I-NEXT: jalr a2
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -25,13 +22,10 @@ define i32 @udiv_constant(i32 %a) nounwi
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(__udivsi3)
; RV32I-NEXT: addi a2, a1, %lo(__udivsi3)
; RV32I-NEXT: addi a1, zero, 5
; RV32I-NEXT: jalr a2
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -42,14 +36,7 @@ define i32 @udiv_constant(i32 %a) nounwi
define i32 @udiv_pow2(i32 %a) nounwind {
; RV32I-LABEL: udiv_pow2:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: srli a0, a0, 3
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = udiv i32 %a, 8
ret i32 %1
@@ -60,12 +47,9 @@ define i64 @udiv64(i64 %a, i64 %b) nounw
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a4, %hi(__udivdi3)
; RV32I-NEXT: addi a4, a4, %lo(__udivdi3)
; RV32I-NEXT: jalr a4
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -78,14 +62,11 @@ define i64 @udiv64_constant(i64 %a) noun
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a2, %hi(__udivdi3)
; RV32I-NEXT: addi a4, a2, %lo(__udivdi3)
; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: jalr a4
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -98,12 +79,9 @@ define i32 @sdiv(i32 %a, i32 %b) nounwin
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a2, %hi(__divsi3)
; RV32I-NEXT: addi a2, a2, %lo(__divsi3)
; RV32I-NEXT: jalr a2
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -116,13 +94,10 @@ define i32 @sdiv_constant(i32 %a) nounwi
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(__divsi3)
; RV32I-NEXT: addi a2, a1, %lo(__divsi3)
; RV32I-NEXT: addi a1, zero, 5
; RV32I-NEXT: jalr a2
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -133,17 +108,10 @@ define i32 @sdiv_constant(i32 %a) nounwi
define i32 @sdiv_pow2(i32 %a) nounwind {
; RV32I-LABEL: sdiv_pow2:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: srli a1, a1, 29
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: srai a0, a0, 3
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = sdiv i32 %a, 8
ret i32 %1
@@ -154,12 +122,9 @@ define i64 @sdiv64(i64 %a, i64 %b) nounw
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a4, %hi(__divdi3)
; RV32I-NEXT: addi a4, a4, %lo(__divdi3)
; RV32I-NEXT: jalr a4
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -172,14 +137,11 @@ define i64 @sdiv64_constant(i64 %a) noun
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a2, %hi(__divdi3)
; RV32I-NEXT: addi a4, a2, %lo(__divdi3)
; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: jalr a4
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Modified: llvm/trunk/test/CodeGen/RISCV/fp128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/fp128.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/fp128.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/fp128.ll Thu Jan 18 03:34:02 2018
@@ -13,48 +13,45 @@ define i32 @test_load_and_cmp() nounwind
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp)
-; RV32I-NEXT: sw s0, 40(sp)
-; RV32I-NEXT: addi s0, sp, 48
; RV32I-NEXT: lui a0, %hi(y+12)
; RV32I-NEXT: addi a0, a0, %lo(y+12)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -28(s0)
+; RV32I-NEXT: sw a0, 20(sp)
; RV32I-NEXT: lui a0, %hi(y+8)
; RV32I-NEXT: addi a0, a0, %lo(y+8)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -32(s0)
+; RV32I-NEXT: sw a0, 16(sp)
; RV32I-NEXT: lui a0, %hi(y+4)
; RV32I-NEXT: addi a0, a0, %lo(y+4)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -36(s0)
+; RV32I-NEXT: sw a0, 12(sp)
; RV32I-NEXT: lui a0, %hi(y)
; RV32I-NEXT: addi a0, a0, %lo(y)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -40(s0)
+; RV32I-NEXT: sw a0, 8(sp)
; RV32I-NEXT: lui a0, %hi(x+12)
; RV32I-NEXT: addi a0, a0, %lo(x+12)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -12(s0)
+; RV32I-NEXT: sw a0, 36(sp)
; RV32I-NEXT: lui a0, %hi(x+8)
; RV32I-NEXT: addi a0, a0, %lo(x+8)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -16(s0)
+; RV32I-NEXT: sw a0, 32(sp)
; RV32I-NEXT: lui a0, %hi(x+4)
; RV32I-NEXT: addi a0, a0, %lo(x+4)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -20(s0)
+; RV32I-NEXT: sw a0, 28(sp)
; RV32I-NEXT: lui a0, %hi(x)
; RV32I-NEXT: addi a0, a0, %lo(x)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -24(s0)
+; RV32I-NEXT: sw a0, 24(sp)
; RV32I-NEXT: lui a0, %hi(__netf2)
; RV32I-NEXT: addi a2, a0, %lo(__netf2)
-; RV32I-NEXT: addi a0, s0, -24
-; RV32I-NEXT: addi a1, s0, -40
+; RV32I-NEXT: addi a0, sp, 24
+; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: jalr a2
; RV32I-NEXT: xor a0, a0, zero
; RV32I-NEXT: snez a0, a0
-; RV32I-NEXT: lw s0, 40(sp)
; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret
@@ -70,59 +67,56 @@ define i32 @test_add_and_fptosi() nounwi
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -80
; RV32I-NEXT: sw ra, 76(sp)
-; RV32I-NEXT: sw s0, 72(sp)
-; RV32I-NEXT: addi s0, sp, 80
; RV32I-NEXT: lui a0, %hi(y+12)
; RV32I-NEXT: addi a0, a0, %lo(y+12)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -44(s0)
+; RV32I-NEXT: sw a0, 36(sp)
; RV32I-NEXT: lui a0, %hi(y+8)
; RV32I-NEXT: addi a0, a0, %lo(y+8)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -48(s0)
+; RV32I-NEXT: sw a0, 32(sp)
; RV32I-NEXT: lui a0, %hi(y+4)
; RV32I-NEXT: addi a0, a0, %lo(y+4)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -52(s0)
+; RV32I-NEXT: sw a0, 28(sp)
; RV32I-NEXT: lui a0, %hi(y)
; RV32I-NEXT: addi a0, a0, %lo(y)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -56(s0)
+; RV32I-NEXT: sw a0, 24(sp)
; RV32I-NEXT: lui a0, %hi(x+12)
; RV32I-NEXT: addi a0, a0, %lo(x+12)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -28(s0)
+; RV32I-NEXT: sw a0, 52(sp)
; RV32I-NEXT: lui a0, %hi(x+8)
; RV32I-NEXT: addi a0, a0, %lo(x+8)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -32(s0)
+; RV32I-NEXT: sw a0, 48(sp)
; RV32I-NEXT: lui a0, %hi(x+4)
; RV32I-NEXT: addi a0, a0, %lo(x+4)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -36(s0)
+; RV32I-NEXT: sw a0, 44(sp)
; RV32I-NEXT: lui a0, %hi(x)
; RV32I-NEXT: addi a0, a0, %lo(x)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -40(s0)
+; RV32I-NEXT: sw a0, 40(sp)
; RV32I-NEXT: lui a0, %hi(__addtf3)
; RV32I-NEXT: addi a3, a0, %lo(__addtf3)
-; RV32I-NEXT: addi a0, s0, -24
-; RV32I-NEXT: addi a1, s0, -40
-; RV32I-NEXT: addi a2, s0, -56
+; RV32I-NEXT: addi a0, sp, 56
+; RV32I-NEXT: addi a1, sp, 40
+; RV32I-NEXT: addi a2, sp, 24
; RV32I-NEXT: jalr a3
-; RV32I-NEXT: lw a0, -12(s0)
-; RV32I-NEXT: sw a0, -60(s0)
-; RV32I-NEXT: lw a0, -16(s0)
-; RV32I-NEXT: sw a0, -64(s0)
-; RV32I-NEXT: lw a0, -20(s0)
-; RV32I-NEXT: sw a0, -68(s0)
-; RV32I-NEXT: lw a0, -24(s0)
-; RV32I-NEXT: sw a0, -72(s0)
+; RV32I-NEXT: lw a0, 68(sp)
+; RV32I-NEXT: sw a0, 20(sp)
+; RV32I-NEXT: lw a0, 64(sp)
+; RV32I-NEXT: sw a0, 16(sp)
+; RV32I-NEXT: lw a0, 60(sp)
+; RV32I-NEXT: sw a0, 12(sp)
+; RV32I-NEXT: lw a0, 56(sp)
+; RV32I-NEXT: sw a0, 8(sp)
; RV32I-NEXT: lui a0, %hi(__fixtfsi)
; RV32I-NEXT: addi a1, a0, %lo(__fixtfsi)
-; RV32I-NEXT: addi a0, s0, -72
+; RV32I-NEXT: addi a0, sp, 8
; RV32I-NEXT: jalr a1
-; RV32I-NEXT: lw s0, 72(sp)
; RV32I-NEXT: lw ra, 76(sp)
; RV32I-NEXT: addi sp, sp, 80
; RV32I-NEXT: ret
Modified: llvm/trunk/test/CodeGen/RISCV/frame.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/frame.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/frame.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/frame.ll Thu Jan 18 03:34:02 2018
@@ -1,30 +1,50 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s
+; RUN: llc -mtriple=riscv32 -disable-fp-elim -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s
%struct.key_t = type { i32, [16 x i8] }
define i32 @test() nounwind {
-; RV32I-LABEL: test:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: addi s0, sp, 32
-; RV32I-NEXT: sw zero, -16(s0)
-; RV32I-NEXT: sw zero, -20(s0)
-; RV32I-NEXT: sw zero, -24(s0)
-; RV32I-NEXT: sw zero, -28(s0)
-; RV32I-NEXT: sw zero, -32(s0)
-; RV32I-NEXT: lui a0, %hi(test1)
-; RV32I-NEXT: addi a1, a0, %lo(test1)
-; RV32I-NEXT: addi a0, s0, -28
-; RV32I-NEXT: jalr a1
-; RV32I-NEXT: mv a0, zero
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: test:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -32
+; RV32I-FPELIM-NEXT: sw ra, 28(sp)
+; RV32I-FPELIM-NEXT: sw zero, 24(sp)
+; RV32I-FPELIM-NEXT: sw zero, 20(sp)
+; RV32I-FPELIM-NEXT: sw zero, 16(sp)
+; RV32I-FPELIM-NEXT: sw zero, 12(sp)
+; RV32I-FPELIM-NEXT: sw zero, 8(sp)
+; RV32I-FPELIM-NEXT: lui a0, %hi(test1)
+; RV32I-FPELIM-NEXT: addi a1, a0, %lo(test1)
+; RV32I-FPELIM-NEXT: addi a0, sp, 12
+; RV32I-FPELIM-NEXT: jalr a1
+; RV32I-FPELIM-NEXT: mv a0, zero
+; RV32I-FPELIM-NEXT: lw ra, 28(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 32
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: test:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -32
+; RV32I-WITHFP-NEXT: sw ra, 28(sp)
+; RV32I-WITHFP-NEXT: sw s0, 24(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 32
+; RV32I-WITHFP-NEXT: sw zero, -16(s0)
+; RV32I-WITHFP-NEXT: sw zero, -20(s0)
+; RV32I-WITHFP-NEXT: sw zero, -24(s0)
+; RV32I-WITHFP-NEXT: sw zero, -28(s0)
+; RV32I-WITHFP-NEXT: sw zero, -32(s0)
+; RV32I-WITHFP-NEXT: lui a0, %hi(test1)
+; RV32I-WITHFP-NEXT: addi a1, a0, %lo(test1)
+; RV32I-WITHFP-NEXT: addi a0, s0, -28
+; RV32I-WITHFP-NEXT: jalr a1
+; RV32I-WITHFP-NEXT: mv a0, zero
+; RV32I-WITHFP-NEXT: lw s0, 24(sp)
+; RV32I-WITHFP-NEXT: lw ra, 28(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 32
+; RV32I-WITHFP-NEXT: ret
%key = alloca %struct.key_t, align 4
%1 = bitcast %struct.key_t* %key to i8*
call void @llvm.memset.p0i8.i64(i8* %1, i8 0, i64 20, i32 4, i1 false)
Modified: llvm/trunk/test/CodeGen/RISCV/frameaddr-returnaddr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/frameaddr-returnaddr.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/frameaddr-returnaddr.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/frameaddr-returnaddr.ll Thu Jan 18 03:34:02 2018
@@ -67,14 +67,7 @@ define i8* @test_frameaddress_3_alloca()
define i8* @test_returnaddress_0() nounwind {
; RV32I-LABEL: test_returnaddress_0:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: mv a0, ra
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = call i8* @llvm.returnaddress(i32 0)
ret i8* %1
Modified: llvm/trunk/test/CodeGen/RISCV/i32-icmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/i32-icmp.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/i32-icmp.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/i32-icmp.ll Thu Jan 18 03:34:02 2018
@@ -8,15 +8,8 @@
define i32 @icmp_eq(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_eq:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp eq i32 %a, %b
%2 = zext i1 %1 to i32
@@ -26,15 +19,8 @@ define i32 @icmp_eq(i32 %a, i32 %b) noun
define i32 @icmp_ne(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_ne:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: snez a0, a0
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp ne i32 %a, %b
%2 = zext i1 %1 to i32
@@ -44,14 +30,7 @@ define i32 @icmp_ne(i32 %a, i32 %b) noun
define i32 @icmp_ugt(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_ugt:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sltu a0, a1, a0
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp ugt i32 %a, %b
%2 = zext i1 %1 to i32
@@ -61,15 +40,8 @@ define i32 @icmp_ugt(i32 %a, i32 %b) nou
define i32 @icmp_uge(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_uge:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sltu a0, a0, a1
; RV32I-NEXT: xori a0, a0, 1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp uge i32 %a, %b
%2 = zext i1 %1 to i32
@@ -79,14 +51,7 @@ define i32 @icmp_uge(i32 %a, i32 %b) nou
define i32 @icmp_ult(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_ult:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sltu a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp ult i32 %a, %b
%2 = zext i1 %1 to i32
@@ -96,15 +61,8 @@ define i32 @icmp_ult(i32 %a, i32 %b) nou
define i32 @icmp_ule(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_ule:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sltu a0, a1, a0
; RV32I-NEXT: xori a0, a0, 1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp ule i32 %a, %b
%2 = zext i1 %1 to i32
@@ -114,14 +72,7 @@ define i32 @icmp_ule(i32 %a, i32 %b) nou
define i32 @icmp_sgt(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_sgt:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slt a0, a1, a0
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp sgt i32 %a, %b
%2 = zext i1 %1 to i32
@@ -131,15 +82,8 @@ define i32 @icmp_sgt(i32 %a, i32 %b) nou
define i32 @icmp_sge(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_sge:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slt a0, a0, a1
; RV32I-NEXT: xori a0, a0, 1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp sge i32 %a, %b
%2 = zext i1 %1 to i32
@@ -149,14 +93,7 @@ define i32 @icmp_sge(i32 %a, i32 %b) nou
define i32 @icmp_slt(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_slt:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slt a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp slt i32 %a, %b
%2 = zext i1 %1 to i32
@@ -166,15 +103,8 @@ define i32 @icmp_slt(i32 %a, i32 %b) nou
define i32 @icmp_sle(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_sle:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slt a0, a1, a0
; RV32I-NEXT: xori a0, a0, 1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp sle i32 %a, %b
%2 = zext i1 %1 to i32
Modified: llvm/trunk/test/CodeGen/RISCV/imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/imm.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/imm.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/imm.ll Thu Jan 18 03:34:02 2018
@@ -7,14 +7,7 @@
define i32 @zero() nounwind {
; RV32I-LABEL: zero:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: mv a0, zero
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
ret i32 0
}
@@ -22,14 +15,7 @@ define i32 @zero() nounwind {
define i32 @pos_small() nounwind {
; RV32I-LABEL: pos_small:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a0, zero, 2047
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
ret i32 2047
}
@@ -37,14 +23,7 @@ define i32 @pos_small() nounwind {
define i32 @neg_small() nounwind {
; RV32I-LABEL: neg_small:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a0, zero, -2048
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
ret i32 -2048
}
@@ -52,15 +31,8 @@ define i32 @neg_small() nounwind {
define i32 @pos_i32() nounwind {
; RV32I-LABEL: pos_i32:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, 423811
; RV32I-NEXT: addi a0, a0, -1297
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
ret i32 1735928559
}
@@ -68,15 +40,8 @@ define i32 @pos_i32() nounwind {
define i32 @neg_i32() nounwind {
; RV32I-LABEL: neg_i32:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, 912092
; RV32I-NEXT: addi a0, a0, -273
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
ret i32 -559038737
}
Modified: llvm/trunk/test/CodeGen/RISCV/indirectbr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/indirectbr.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/indirectbr.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/indirectbr.ll Thu Jan 18 03:34:02 2018
@@ -7,12 +7,9 @@ define i32 @indirectbr(i8* %target) noun
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: jr a0
; RV32I-NEXT: .LBB0_1: # %ret
; RV32I-NEXT: mv a0, zero
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -28,12 +25,9 @@ define i32 @indirectbr_with_offset(i8* %
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: jalr zero, a0, 1380
; RV32I-NEXT: .LBB1_1: # %ret
; RV32I-NEXT: mv a0, zero
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Modified: llvm/trunk/test/CodeGen/RISCV/inline-asm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/inline-asm.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/inline-asm.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/inline-asm.ll Thu Jan 18 03:34:02 2018
@@ -7,19 +7,12 @@
define i32 @constraint_r(i32 %a) {
; RV32I-LABEL: constraint_r:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(gi)
; RV32I-NEXT: addi a1, a1, %lo(gi)
; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: #APP
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: #NO_APP
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = load i32, i32* @gi
%2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1)
@@ -29,16 +22,9 @@ define i32 @constraint_r(i32 %a) {
define i32 @constraint_i(i32 %a) {
; RV32I-LABEL: constraint_i:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, a0, 113
; RV32I-NEXT: #NO_APP
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = load i32, i32* @gi
%2 = tail call i32 asm "addi $0, $1, $2", "=r,r,i"(i32 %a, i32 113)
@@ -48,15 +34,8 @@ define i32 @constraint_i(i32 %a) {
define void @constraint_m(i32* %a) {
; RV32I-LABEL: constraint_m:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: #APP
; RV32I-NEXT: #NO_APP
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
call void asm sideeffect "", "=*m"(i32* %a)
ret void
@@ -65,16 +44,9 @@ define void @constraint_m(i32* %a) {
define i32 @constraint_m2(i32* %a) {
; RV32I-LABEL: constraint_m2:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: #APP
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: #NO_APP
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = tail call i32 asm "lw $0, $1", "=r,*m"(i32* %a) nounwind
ret i32 %1
Modified: llvm/trunk/test/CodeGen/RISCV/jumptable.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/jumptable.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/jumptable.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/jumptable.ll Thu Jan 18 03:34:02 2018
@@ -5,10 +5,6 @@
define void @jt(i32 %in, i32* %out) {
; RV32I-LABEL: jt:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: blt a2, a0, .LBB0_4
; RV32I-NEXT: # %bb.1: # %entry
@@ -19,7 +15,7 @@ define void @jt(i32 %in, i32* %out) {
; RV32I-NEXT: # %bb.3: # %bb2
; RV32I-NEXT: addi a0, zero, 3
; RV32I-NEXT: sw a0, 0(a1)
-; RV32I-NEXT: j .LBB0_9
+; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_4: # %entry
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: beq a0, a3, .LBB0_8
@@ -29,17 +25,14 @@ define void @jt(i32 %in, i32* %out) {
; RV32I-NEXT: # %bb.6: # %bb4
; RV32I-NEXT: addi a0, zero, 1
; RV32I-NEXT: sw a0, 0(a1)
-; RV32I-NEXT: j .LBB0_9
+; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_7: # %bb1
; RV32I-NEXT: addi a0, zero, 4
; RV32I-NEXT: sw a0, 0(a1)
-; RV32I-NEXT: j .LBB0_9
+; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_8: # %bb3
; RV32I-NEXT: sw a2, 0(a1)
; RV32I-NEXT: .LBB0_9: # %exit
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
entry:
switch i32 %in, label %exit [
Modified: llvm/trunk/test/CodeGen/RISCV/large-stack.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/large-stack.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/large-stack.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/large-stack.ll Thu Jan 18 03:34:02 2018
@@ -1,38 +1,50 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs -disable-fp-elim < %s \
+; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s
; TODO: the quality of the generated code is poor
define void @test() nounwind {
-; RV32I-LABEL: test:
-; RV32I: # %bb.0:
-; RV32I-NEXT: lui a0, 74565
-; RV32I-NEXT: addi a0, a0, 1680
-; RV32I-NEXT: sub sp, sp, a0
-; RV32I-NEXT: lui a0, 74565
-; RV32I-NEXT: addi a0, a0, 1676
-; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: sw ra, 0(a0)
-; RV32I-NEXT: lui a0, 74565
-; RV32I-NEXT: addi a0, a0, 1672
-; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: sw s0, 0(a0)
-; RV32I-NEXT: lui a0, 74565
-; RV32I-NEXT: addi a0, a0, 1680
-; RV32I-NEXT: add s0, sp, a0
-; RV32I-NEXT: lui a0, 74565
-; RV32I-NEXT: addi a0, a0, 1672
-; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: lw s0, 0(a0)
-; RV32I-NEXT: lui a0, 74565
-; RV32I-NEXT: addi a0, a0, 1676
-; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: lw ra, 0(a0)
-; RV32I-NEXT: lui a0, 74565
-; RV32I-NEXT: addi a0, a0, 1680
-; RV32I-NEXT: add sp, sp, a0
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: test:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: lui a0, 74565
+; RV32I-FPELIM-NEXT: addi a0, a0, 1664
+; RV32I-FPELIM-NEXT: sub sp, sp, a0
+; RV32I-FPELIM-NEXT: lui a0, 74565
+; RV32I-FPELIM-NEXT: addi a0, a0, 1664
+; RV32I-FPELIM-NEXT: add sp, sp, a0
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: test:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: lui a0, 74565
+; RV32I-WITHFP-NEXT: addi a0, a0, 1680
+; RV32I-WITHFP-NEXT: sub sp, sp, a0
+; RV32I-WITHFP-NEXT: lui a0, 74565
+; RV32I-WITHFP-NEXT: addi a0, a0, 1676
+; RV32I-WITHFP-NEXT: add a0, sp, a0
+; RV32I-WITHFP-NEXT: sw ra, 0(a0)
+; RV32I-WITHFP-NEXT: lui a0, 74565
+; RV32I-WITHFP-NEXT: addi a0, a0, 1672
+; RV32I-WITHFP-NEXT: add a0, sp, a0
+; RV32I-WITHFP-NEXT: sw s0, 0(a0)
+; RV32I-WITHFP-NEXT: lui a0, 74565
+; RV32I-WITHFP-NEXT: addi a0, a0, 1680
+; RV32I-WITHFP-NEXT: add s0, sp, a0
+; RV32I-WITHFP-NEXT: lui a0, 74565
+; RV32I-WITHFP-NEXT: addi a0, a0, 1672
+; RV32I-WITHFP-NEXT: add a0, sp, a0
+; RV32I-WITHFP-NEXT: lw s0, 0(a0)
+; RV32I-WITHFP-NEXT: lui a0, 74565
+; RV32I-WITHFP-NEXT: addi a0, a0, 1676
+; RV32I-WITHFP-NEXT: add a0, sp, a0
+; RV32I-WITHFP-NEXT: lw ra, 0(a0)
+; RV32I-WITHFP-NEXT: lui a0, 74565
+; RV32I-WITHFP-NEXT: addi a0, a0, 1680
+; RV32I-WITHFP-NEXT: add sp, sp, a0
+; RV32I-WITHFP-NEXT: ret
%tmp = alloca [ 305419896 x i8 ] , align 4
ret void
}
@@ -41,64 +53,101 @@ define void @test() nounwind {
; use of the emergency spill slot.
define void @test_emergency_spill_slot(i32 %a) nounwind {
-; RV32I-LABEL: test_emergency_spill_slot:
-; RV32I: # %bb.0:
-; RV32I-NEXT: lui a1, 98
-; RV32I-NEXT: addi a1, a1, -1376
-; RV32I-NEXT: sub sp, sp, a1
-; RV32I-NEXT: lui a1, 98
-; RV32I-NEXT: addi a1, a1, -1380
-; RV32I-NEXT: add a1, sp, a1
-; RV32I-NEXT: sw ra, 0(a1)
-; RV32I-NEXT: lui a1, 98
-; RV32I-NEXT: addi a1, a1, -1384
-; RV32I-NEXT: add a1, sp, a1
-; RV32I-NEXT: sw s0, 0(a1)
-; RV32I-NEXT: lui a1, 98
-; RV32I-NEXT: addi a1, a1, -1388
-; RV32I-NEXT: add a1, sp, a1
-; RV32I-NEXT: sw s1, 0(a1)
-; RV32I-NEXT: lui a1, 98
-; RV32I-NEXT: addi a1, a1, -1392
-; RV32I-NEXT: add a1, sp, a1
-; RV32I-NEXT: sw s2, 0(a1)
-; RV32I-NEXT: lui a1, 98
-; RV32I-NEXT: addi a1, a1, -1376
-; RV32I-NEXT: add s0, sp, a1
-; RV32I-NEXT: lui a1, 78
-; RV32I-NEXT: addi a1, a1, 512
-; RV32I-NEXT: lui a2, 1048478
-; RV32I-NEXT: addi a2, a2, 1388
-; RV32I-NEXT: add a2, s0, a2
-; RV32I-NEXT: mv a2, a2
-; RV32I-NEXT: add a1, a2, a1
-; RV32I-NEXT: #APP
-; RV32I-NEXT: nop
-; RV32I-NEXT: #NO_APP
-; RV32I-NEXT: sw a0, 0(a1)
-; RV32I-NEXT: #APP
-; RV32I-NEXT: nop
-; RV32I-NEXT: #NO_APP
-; RV32I-NEXT: lui a0, 98
-; RV32I-NEXT: addi a0, a0, -1392
-; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: lw s2, 0(a0)
-; RV32I-NEXT: lui a0, 98
-; RV32I-NEXT: addi a0, a0, -1388
-; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: lw s1, 0(a0)
-; RV32I-NEXT: lui a0, 98
-; RV32I-NEXT: addi a0, a0, -1384
-; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: lw s0, 0(a0)
-; RV32I-NEXT: lui a0, 98
-; RV32I-NEXT: addi a0, a0, -1380
-; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: lw ra, 0(a0)
-; RV32I-NEXT: lui a0, 98
-; RV32I-NEXT: addi a0, a0, -1376
-; RV32I-NEXT: add sp, sp, a0
-; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: test_emergency_spill_slot:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: lui a1, 98
+; RV32I-FPELIM-NEXT: addi a1, a1, -1392
+; RV32I-FPELIM-NEXT: sub sp, sp, a1
+; RV32I-FPELIM-NEXT: lui a1, 98
+; RV32I-FPELIM-NEXT: addi a1, a1, -1396
+; RV32I-FPELIM-NEXT: add a1, sp, a1
+; RV32I-FPELIM-NEXT: sw s1, 0(a1)
+; RV32I-FPELIM-NEXT: lui a1, 98
+; RV32I-FPELIM-NEXT: addi a1, a1, -1400
+; RV32I-FPELIM-NEXT: add a1, sp, a1
+; RV32I-FPELIM-NEXT: sw s2, 0(a1)
+; RV32I-FPELIM-NEXT: lui a1, 78
+; RV32I-FPELIM-NEXT: addi a1, a1, 512
+; RV32I-FPELIM-NEXT: addi a2, sp, 8
+; RV32I-FPELIM-NEXT: add a1, a2, a1
+; RV32I-FPELIM-NEXT: #APP
+; RV32I-FPELIM-NEXT: nop
+; RV32I-FPELIM-NEXT: #NO_APP
+; RV32I-FPELIM-NEXT: sw a0, 0(a1)
+; RV32I-FPELIM-NEXT: #APP
+; RV32I-FPELIM-NEXT: nop
+; RV32I-FPELIM-NEXT: #NO_APP
+; RV32I-FPELIM-NEXT: lui a0, 98
+; RV32I-FPELIM-NEXT: addi a0, a0, -1400
+; RV32I-FPELIM-NEXT: add a0, sp, a0
+; RV32I-FPELIM-NEXT: lw s2, 0(a0)
+; RV32I-FPELIM-NEXT: lui a0, 98
+; RV32I-FPELIM-NEXT: addi a0, a0, -1396
+; RV32I-FPELIM-NEXT: add a0, sp, a0
+; RV32I-FPELIM-NEXT: lw s1, 0(a0)
+; RV32I-FPELIM-NEXT: lui a0, 98
+; RV32I-FPELIM-NEXT: addi a0, a0, -1392
+; RV32I-FPELIM-NEXT: add sp, sp, a0
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: test_emergency_spill_slot:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: lui a1, 98
+; RV32I-WITHFP-NEXT: addi a1, a1, -1376
+; RV32I-WITHFP-NEXT: sub sp, sp, a1
+; RV32I-WITHFP-NEXT: lui a1, 98
+; RV32I-WITHFP-NEXT: addi a1, a1, -1380
+; RV32I-WITHFP-NEXT: add a1, sp, a1
+; RV32I-WITHFP-NEXT: sw ra, 0(a1)
+; RV32I-WITHFP-NEXT: lui a1, 98
+; RV32I-WITHFP-NEXT: addi a1, a1, -1384
+; RV32I-WITHFP-NEXT: add a1, sp, a1
+; RV32I-WITHFP-NEXT: sw s0, 0(a1)
+; RV32I-WITHFP-NEXT: lui a1, 98
+; RV32I-WITHFP-NEXT: addi a1, a1, -1388
+; RV32I-WITHFP-NEXT: add a1, sp, a1
+; RV32I-WITHFP-NEXT: sw s1, 0(a1)
+; RV32I-WITHFP-NEXT: lui a1, 98
+; RV32I-WITHFP-NEXT: addi a1, a1, -1392
+; RV32I-WITHFP-NEXT: add a1, sp, a1
+; RV32I-WITHFP-NEXT: sw s2, 0(a1)
+; RV32I-WITHFP-NEXT: lui a1, 98
+; RV32I-WITHFP-NEXT: addi a1, a1, -1376
+; RV32I-WITHFP-NEXT: add s0, sp, a1
+; RV32I-WITHFP-NEXT: lui a1, 78
+; RV32I-WITHFP-NEXT: addi a1, a1, 512
+; RV32I-WITHFP-NEXT: lui a2, 1048478
+; RV32I-WITHFP-NEXT: addi a2, a2, 1388
+; RV32I-WITHFP-NEXT: add a2, s0, a2
+; RV32I-WITHFP-NEXT: mv a2, a2
+; RV32I-WITHFP-NEXT: add a1, a2, a1
+; RV32I-WITHFP-NEXT: #APP
+; RV32I-WITHFP-NEXT: nop
+; RV32I-WITHFP-NEXT: #NO_APP
+; RV32I-WITHFP-NEXT: sw a0, 0(a1)
+; RV32I-WITHFP-NEXT: #APP
+; RV32I-WITHFP-NEXT: nop
+; RV32I-WITHFP-NEXT: #NO_APP
+; RV32I-WITHFP-NEXT: lui a0, 98
+; RV32I-WITHFP-NEXT: addi a0, a0, -1392
+; RV32I-WITHFP-NEXT: add a0, sp, a0
+; RV32I-WITHFP-NEXT: lw s2, 0(a0)
+; RV32I-WITHFP-NEXT: lui a0, 98
+; RV32I-WITHFP-NEXT: addi a0, a0, -1388
+; RV32I-WITHFP-NEXT: add a0, sp, a0
+; RV32I-WITHFP-NEXT: lw s1, 0(a0)
+; RV32I-WITHFP-NEXT: lui a0, 98
+; RV32I-WITHFP-NEXT: addi a0, a0, -1384
+; RV32I-WITHFP-NEXT: add a0, sp, a0
+; RV32I-WITHFP-NEXT: lw s0, 0(a0)
+; RV32I-WITHFP-NEXT: lui a0, 98
+; RV32I-WITHFP-NEXT: addi a0, a0, -1380
+; RV32I-WITHFP-NEXT: add a0, sp, a0
+; RV32I-WITHFP-NEXT: lw ra, 0(a0)
+; RV32I-WITHFP-NEXT: lui a0, 98
+; RV32I-WITHFP-NEXT: addi a0, a0, -1376
+; RV32I-WITHFP-NEXT: add sp, sp, a0
+; RV32I-WITHFP-NEXT: ret
%data = alloca [ 100000 x i32 ] , align 4
%ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %data, i32 0, i32 80000
%1 = tail call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "nop", "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r"()
Modified: llvm/trunk/test/CodeGen/RISCV/mem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/mem.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/mem.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/mem.ll Thu Jan 18 03:34:02 2018
@@ -7,15 +7,8 @@
define i32 @lb(i8 *%a) nounwind {
; RV32I-LABEL: lb:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lb a1, 0(a0)
; RV32I-NEXT: lb a0, 1(a0)
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = getelementptr i8, i8* %a, i32 1
%2 = load i8, i8* %1
@@ -28,15 +21,8 @@ define i32 @lb(i8 *%a) nounwind {
define i32 @lh(i16 *%a) nounwind {
; RV32I-LABEL: lh:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lh a1, 0(a0)
; RV32I-NEXT: lh a0, 4(a0)
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = getelementptr i16, i16* %a, i32 2
%2 = load i16, i16* %1
@@ -49,15 +35,8 @@ define i32 @lh(i16 *%a) nounwind {
define i32 @lw(i32 *%a) nounwind {
; RV32I-LABEL: lw:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw a1, 0(a0)
; RV32I-NEXT: lw a0, 12(a0)
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = getelementptr i32, i32* %a, i32 3
%2 = load i32, i32* %1
@@ -68,16 +47,9 @@ define i32 @lw(i32 *%a) nounwind {
define i32 @lbu(i8 *%a) nounwind {
; RV32I-LABEL: lbu:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lbu a1, 0(a0)
; RV32I-NEXT: lbu a0, 4(a0)
; RV32I-NEXT: add a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = getelementptr i8, i8* %a, i32 4
%2 = load i8, i8* %1
@@ -91,16 +63,9 @@ define i32 @lbu(i8 *%a) nounwind {
define i32 @lhu(i16 *%a) nounwind {
; RV32I-LABEL: lhu:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lhu a0, 10(a0)
; RV32I-NEXT: add a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = getelementptr i16, i16* %a, i32 5
%2 = load i16, i16* %1
@@ -116,15 +81,8 @@ define i32 @lhu(i16 *%a) nounwind {
define void @sb(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: sb:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sb a1, 6(a0)
; RV32I-NEXT: sb a1, 0(a0)
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
store i8 %b, i8* %a
%1 = getelementptr i8, i8* %a, i32 6
@@ -135,15 +93,8 @@ define void @sb(i8 *%a, i8 %b) nounwind
define void @sh(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: sh:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sh a1, 14(a0)
; RV32I-NEXT: sh a1, 0(a0)
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
store i16 %b, i16* %a
%1 = getelementptr i16, i16* %a, i32 7
@@ -154,15 +105,8 @@ define void @sh(i16 *%a, i16 %b) nounwin
define void @sw(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: sw:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sw a1, 32(a0)
; RV32I-NEXT: sw a1, 0(a0)
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
store i32 %b, i32* %a
%1 = getelementptr i32, i32* %a, i32 8
@@ -174,17 +118,10 @@ define void @sw(i32 *%a, i32 %b) nounwin
define i32 @load_sext_zext_anyext_i1(i1 *%a) nounwind {
; RV32I-LABEL: load_sext_zext_anyext_i1:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lb a1, 0(a0)
; RV32I-NEXT: lbu a1, 1(a0)
; RV32I-NEXT: lbu a0, 2(a0)
; RV32I-NEXT: sub a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; sextload i1
%1 = getelementptr i1, i1* %a, i32 1
@@ -203,17 +140,10 @@ define i32 @load_sext_zext_anyext_i1(i1
define i16 @load_sext_zext_anyext_i1_i16(i1 *%a) nounwind {
; RV32I-LABEL: load_sext_zext_anyext_i1_i16:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lb a1, 0(a0)
; RV32I-NEXT: lbu a1, 1(a0)
; RV32I-NEXT: lbu a0, 2(a0)
; RV32I-NEXT: sub a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; sextload i1
%1 = getelementptr i1, i1* %a, i32 1
@@ -236,10 +166,6 @@ define i32 @lw_sw_global(i32 %a) nounwin
; TODO: the addi should be folded in to the lw/sw operations
; RV32I-LABEL: lw_sw_global:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(G)
; RV32I-NEXT: addi a2, a1, %lo(G)
; RV32I-NEXT: lw a1, 0(a2)
@@ -249,9 +175,6 @@ define i32 @lw_sw_global(i32 %a) nounwin
; RV32I-NEXT: lw a3, 0(a2)
; RV32I-NEXT: sw a0, 0(a2)
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = load volatile i32, i32* @G
store i32 %a, i32* @G
@@ -266,18 +189,11 @@ define i32 @lw_sw_constant(i32 %a) nounw
; TODO: the addi should be folded in to the lw/sw
; RV32I-LABEL: lw_sw_constant:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, 912092
; RV32I-NEXT: addi a2, a1, -273
; RV32I-NEXT: lw a1, 0(a2)
; RV32I-NEXT: sw a0, 0(a2)
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = inttoptr i32 3735928559 to i32*
%2 = load volatile i32, i32* %1
Modified: llvm/trunk/test/CodeGen/RISCV/mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/mul.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/mul.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/mul.ll Thu Jan 18 03:34:02 2018
@@ -7,13 +7,10 @@ define i32 @square(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(__mulsi3)
; RV32I-NEXT: addi a2, a1, %lo(__mulsi3)
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: jalr a2
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -26,12 +23,9 @@ define i32 @mul(i32 %a, i32 %b) nounwind
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a2, %hi(__mulsi3)
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
; RV32I-NEXT: jalr a2
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -44,13 +38,10 @@ define i32 @mul_constant(i32 %a) nounwin
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(__mulsi3)
; RV32I-NEXT: addi a2, a1, %lo(__mulsi3)
; RV32I-NEXT: addi a1, zero, 5
; RV32I-NEXT: jalr a2
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -61,14 +52,7 @@ define i32 @mul_constant(i32 %a) nounwin
define i32 @mul_pow2(i32 %a) nounwind {
; RV32I-LABEL: mul_pow2:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slli a0, a0, 3
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = mul i32 %a, 8
ret i32 %1
@@ -79,12 +63,9 @@ define i64 @mul64(i64 %a, i64 %b) nounwi
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a4, %hi(__muldi3)
; RV32I-NEXT: addi a4, a4, %lo(__muldi3)
; RV32I-NEXT: jalr a4
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -97,14 +78,11 @@ define i64 @mul64_constant(i64 %a) nounw
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a2, %hi(__muldi3)
; RV32I-NEXT: addi a4, a2, %lo(__muldi3)
; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: jalr a4
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Modified: llvm/trunk/test/CodeGen/RISCV/rem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/rem.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/rem.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/rem.ll Thu Jan 18 03:34:02 2018
@@ -7,12 +7,9 @@ define i32 @urem(i32 %a, i32 %b) nounwin
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a2, %hi(__umodsi3)
; RV32I-NEXT: addi a2, a2, %lo(__umodsi3)
; RV32I-NEXT: jalr a2
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -25,12 +22,9 @@ define i32 @srem(i32 %a, i32 %b) nounwin
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a2, %hi(__modsi3)
; RV32I-NEXT: addi a2, a2, %lo(__modsi3)
; RV32I-NEXT: jalr a2
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Modified: llvm/trunk/test/CodeGen/RISCV/rotl-rotr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/rotl-rotr.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/rotl-rotr.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/rotl-rotr.ll Thu Jan 18 03:34:02 2018
@@ -8,18 +8,11 @@
define i32 @rotl(i32 %x, i32 %y) {
; RV32I-LABEL: rotl:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a2, zero, 32
; RV32I-NEXT: sub a2, a2, a1
; RV32I-NEXT: sll a1, a0, a1
; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: or a0, a1, a0
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%z = sub i32 32, %y
%b = shl i32 %x, %y
@@ -31,18 +24,11 @@ define i32 @rotl(i32 %x, i32 %y) {
define i32 @rotr(i32 %x, i32 %y) {
; RV32I-LABEL: rotr:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a2, zero, 32
; RV32I-NEXT: sub a2, a2, a1
; RV32I-NEXT: srl a1, a0, a1
; RV32I-NEXT: sll a0, a0, a2
; RV32I-NEXT: or a0, a1, a0
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%z = sub i32 32, %y
%b = lshr i32 %x, %y
Modified: llvm/trunk/test/CodeGen/RISCV/select-cc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/select-cc.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/select-cc.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/select-cc.ll Thu Jan 18 03:34:02 2018
@@ -5,10 +5,6 @@
define i32 @foo(i32 %a, i32 *%b) {
; RV32I-LABEL: foo:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: beq a0, a2, .LBB0_2
; RV32I-NEXT: # %bb.1:
@@ -59,9 +55,6 @@ define i32 @foo(i32 %a, i32 *%b) {
; RV32I-NEXT: # %bb.19:
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB0_20:
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%val1 = load volatile i32, i32* %b
%tst1 = icmp eq i32 %a, %val1
Modified: llvm/trunk/test/CodeGen/RISCV/sext-zext-trunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/sext-zext-trunc.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/sext-zext-trunc.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/sext-zext-trunc.ll Thu Jan 18 03:34:02 2018
@@ -5,15 +5,8 @@
define i8 @sext_i1_to_i8(i1 %a) {
; RV32I-LABEL: sext_i1_to_i8:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: neg a0, a0
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = sext i1 %a to i8
ret i8 %1
@@ -22,15 +15,8 @@ define i8 @sext_i1_to_i8(i1 %a) {
define i16 @sext_i1_to_i16(i1 %a) {
; RV32I-LABEL: sext_i1_to_i16:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: neg a0, a0
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = sext i1 %a to i16
ret i16 %1
@@ -39,15 +25,8 @@ define i16 @sext_i1_to_i16(i1 %a) {
define i32 @sext_i1_to_i32(i1 %a) {
; RV32I-LABEL: sext_i1_to_i32:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: neg a0, a0
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = sext i1 %a to i32
ret i32 %1
@@ -56,16 +35,9 @@ define i32 @sext_i1_to_i32(i1 %a) {
define i64 @sext_i1_to_i64(i1 %a) {
; RV32I-LABEL: sext_i1_to_i64:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = sext i1 %a to i64
ret i64 %1
@@ -74,15 +46,8 @@ define i64 @sext_i1_to_i64(i1 %a) {
define i16 @sext_i8_to_i16(i8 %a) {
; RV32I-LABEL: sext_i8_to_i16:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = sext i8 %a to i16
ret i16 %1
@@ -91,15 +56,8 @@ define i16 @sext_i8_to_i16(i8 %a) {
define i32 @sext_i8_to_i32(i8 %a) {
; RV32I-LABEL: sext_i8_to_i32:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = sext i8 %a to i32
ret i32 %1
@@ -108,16 +66,9 @@ define i32 @sext_i8_to_i32(i8 %a) {
define i64 @sext_i8_to_i64(i8 %a) {
; RV32I-LABEL: sext_i8_to_i64:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slli a1, a0, 24
; RV32I-NEXT: srai a0, a1, 24
; RV32I-NEXT: srai a1, a1, 31
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = sext i8 %a to i64
ret i64 %1
@@ -126,15 +77,8 @@ define i64 @sext_i8_to_i64(i8 %a) {
define i32 @sext_i16_to_i32(i16 %a) {
; RV32I-LABEL: sext_i16_to_i32:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = sext i16 %a to i32
ret i32 %1
@@ -143,16 +87,9 @@ define i32 @sext_i16_to_i32(i16 %a) {
define i64 @sext_i16_to_i64(i16 %a) {
; RV32I-LABEL: sext_i16_to_i64:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slli a1, a0, 16
; RV32I-NEXT: srai a0, a1, 16
; RV32I-NEXT: srai a1, a1, 31
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = sext i16 %a to i64
ret i64 %1
@@ -161,14 +98,7 @@ define i64 @sext_i16_to_i64(i16 %a) {
define i64 @sext_i32_to_i64(i32 %a) {
; RV32I-LABEL: sext_i32_to_i64:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: srai a1, a0, 31
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = sext i32 %a to i64
ret i64 %1
@@ -177,14 +107,7 @@ define i64 @sext_i32_to_i64(i32 %a) {
define i8 @zext_i1_to_i8(i1 %a) {
; RV32I-LABEL: zext_i1_to_i8:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = zext i1 %a to i8
ret i8 %1
@@ -193,14 +116,7 @@ define i8 @zext_i1_to_i8(i1 %a) {
define i16 @zext_i1_to_i16(i1 %a) {
; RV32I-LABEL: zext_i1_to_i16:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = zext i1 %a to i16
ret i16 %1
@@ -209,14 +125,7 @@ define i16 @zext_i1_to_i16(i1 %a) {
define i32 @zext_i1_to_i32(i1 %a) {
; RV32I-LABEL: zext_i1_to_i32:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = zext i1 %a to i32
ret i32 %1
@@ -225,15 +134,8 @@ define i32 @zext_i1_to_i32(i1 %a) {
define i64 @zext_i1_to_i64(i1 %a) {
; RV32I-LABEL: zext_i1_to_i64:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: mv a1, zero
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = zext i1 %a to i64
ret i64 %1
@@ -242,14 +144,7 @@ define i64 @zext_i1_to_i64(i1 %a) {
define i16 @zext_i8_to_i16(i8 %a) {
; RV32I-LABEL: zext_i8_to_i16:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 255
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = zext i8 %a to i16
ret i16 %1
@@ -258,14 +153,7 @@ define i16 @zext_i8_to_i16(i8 %a) {
define i32 @zext_i8_to_i32(i8 %a) {
; RV32I-LABEL: zext_i8_to_i32:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 255
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = zext i8 %a to i32
ret i32 %1
@@ -274,15 +162,8 @@ define i32 @zext_i8_to_i32(i8 %a) {
define i64 @zext_i8_to_i64(i8 %a) {
; RV32I-LABEL: zext_i8_to_i64:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: mv a1, zero
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = zext i8 %a to i64
ret i64 %1
@@ -291,16 +172,9 @@ define i64 @zext_i8_to_i64(i8 %a) {
define i32 @zext_i16_to_i32(i16 %a) {
; RV32I-LABEL: zext_i16_to_i32:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = zext i16 %a to i32
ret i32 %1
@@ -309,17 +183,10 @@ define i32 @zext_i16_to_i32(i16 %a) {
define i64 @zext_i16_to_i64(i16 %a) {
; RV32I-LABEL: zext_i16_to_i64:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: mv a1, zero
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = zext i16 %a to i64
ret i64 %1
@@ -328,14 +195,7 @@ define i64 @zext_i16_to_i64(i16 %a) {
define i64 @zext_i32_to_i64(i32 %a) {
; RV32I-LABEL: zext_i32_to_i64:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: mv a1, zero
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = zext i32 %a to i64
ret i64 %1
@@ -347,13 +207,6 @@ define i64 @zext_i32_to_i64(i32 %a) {
define i1 @trunc_i8_to_i1(i8 %a) {
; RV32I-LABEL: trunc_i8_to_i1:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = trunc i8 %a to i1
ret i1 %1
@@ -362,13 +215,6 @@ define i1 @trunc_i8_to_i1(i8 %a) {
define i1 @trunc_i16_to_i1(i16 %a) {
; RV32I-LABEL: trunc_i16_to_i1:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = trunc i16 %a to i1
ret i1 %1
@@ -377,13 +223,6 @@ define i1 @trunc_i16_to_i1(i16 %a) {
define i1 @trunc_i32_to_i1(i32 %a) {
; RV32I-LABEL: trunc_i32_to_i1:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = trunc i32 %a to i1
ret i1 %1
@@ -392,13 +231,6 @@ define i1 @trunc_i32_to_i1(i32 %a) {
define i1 @trunc_i64_to_i1(i64 %a) {
; RV32I-LABEL: trunc_i64_to_i1:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = trunc i64 %a to i1
ret i1 %1
@@ -407,13 +239,6 @@ define i1 @trunc_i64_to_i1(i64 %a) {
define i8 @trunc_i16_to_i8(i16 %a) {
; RV32I-LABEL: trunc_i16_to_i8:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = trunc i16 %a to i8
ret i8 %1
@@ -422,13 +247,6 @@ define i8 @trunc_i16_to_i8(i16 %a) {
define i8 @trunc_i32_to_i8(i32 %a) {
; RV32I-LABEL: trunc_i32_to_i8:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = trunc i32 %a to i8
ret i8 %1
@@ -437,13 +255,6 @@ define i8 @trunc_i32_to_i8(i32 %a) {
define i8 @trunc_i64_to_i8(i64 %a) {
; RV32I-LABEL: trunc_i64_to_i8:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = trunc i64 %a to i8
ret i8 %1
@@ -452,13 +263,6 @@ define i8 @trunc_i64_to_i8(i64 %a) {
define i16 @trunc_i32_to_i16(i32 %a) {
; RV32I-LABEL: trunc_i32_to_i16:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = trunc i32 %a to i16
ret i16 %1
@@ -467,13 +271,6 @@ define i16 @trunc_i32_to_i16(i32 %a) {
define i16 @trunc_i64_to_i16(i64 %a) {
; RV32I-LABEL: trunc_i64_to_i16:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = trunc i64 %a to i16
ret i16 %1
@@ -482,13 +279,6 @@ define i16 @trunc_i64_to_i16(i64 %a) {
define i32 @trunc_i64_to_i32(i64 %a) {
; RV32I-LABEL: trunc_i64_to_i32:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = trunc i64 %a to i32
ret i32 %1
Modified: llvm/trunk/test/CodeGen/RISCV/shifts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/shifts.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/shifts.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/shifts.ll Thu Jan 18 03:34:02 2018
@@ -10,12 +10,9 @@ define i64 @lshr64(i64 %a, i64 %b) nounw
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a3, %hi(__lshrdi3)
; RV32I-NEXT: addi a3, a3, %lo(__lshrdi3)
; RV32I-NEXT: jalr a3
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -28,12 +25,9 @@ define i64 @ashr64(i64 %a, i64 %b) nounw
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a3, %hi(__ashrdi3)
; RV32I-NEXT: addi a3, a3, %lo(__ashrdi3)
; RV32I-NEXT: jalr a3
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -46,12 +40,9 @@ define i64 @shl64(i64 %a, i64 %b) nounwi
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a3, %hi(__ashldi3)
; RV32I-NEXT: addi a3, a3, %lo(__ashldi3)
; RV32I-NEXT: jalr a3
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Modified: llvm/trunk/test/CodeGen/RISCV/vararg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/vararg.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/vararg.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/vararg.ll Thu Jan 18 03:34:02 2018
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs -disable-fp-elim < %s \
+; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s
declare void @llvm.va_start(i8*)
declare void @llvm.va_end(i8*)
@@ -15,23 +17,54 @@ define i32 @va1(i8* %fmt, ...) nounwind
; RV32I-LABEL: va1:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: sw a1, 4(s0)
-; RV32I-NEXT: sw a7, 28(s0)
-; RV32I-NEXT: sw a6, 24(s0)
-; RV32I-NEXT: sw a5, 20(s0)
-; RV32I-NEXT: sw a4, 16(s0)
-; RV32I-NEXT: sw a3, 12(s0)
-; RV32I-NEXT: sw a2, 8(s0)
-; RV32I-NEXT: addi a0, s0, 8
-; RV32I-NEXT: sw a0, -12(s0)
-; RV32I-NEXT: lw a0, 4(s0)
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: sw a1, 20(sp)
+; RV32I-NEXT: sw a7, 44(sp)
+; RV32I-NEXT: sw a6, 40(sp)
+; RV32I-NEXT: sw a5, 36(sp)
+; RV32I-NEXT: sw a4, 32(sp)
+; RV32I-NEXT: sw a3, 28(sp)
+; RV32I-NEXT: sw a2, 24(sp)
+; RV32I-NEXT: addi a0, sp, 24
+; RV32I-NEXT: sw a0, 12(sp)
+; RV32I-NEXT: lw a0, 20(sp)
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: va1:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -48
+; RV32I-FPELIM-NEXT: sw a1, 20(sp)
+; RV32I-FPELIM-NEXT: sw a7, 44(sp)
+; RV32I-FPELIM-NEXT: sw a6, 40(sp)
+; RV32I-FPELIM-NEXT: sw a5, 36(sp)
+; RV32I-FPELIM-NEXT: sw a4, 32(sp)
+; RV32I-FPELIM-NEXT: sw a3, 28(sp)
+; RV32I-FPELIM-NEXT: sw a2, 24(sp)
+; RV32I-FPELIM-NEXT: addi a0, sp, 24
+; RV32I-FPELIM-NEXT: sw a0, 12(sp)
+; RV32I-FPELIM-NEXT: lw a0, 20(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 48
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: va1:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -48
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: sw a1, 4(s0)
+; RV32I-WITHFP-NEXT: sw a7, 28(s0)
+; RV32I-WITHFP-NEXT: sw a6, 24(s0)
+; RV32I-WITHFP-NEXT: sw a5, 20(s0)
+; RV32I-WITHFP-NEXT: sw a4, 16(s0)
+; RV32I-WITHFP-NEXT: sw a3, 12(s0)
+; RV32I-WITHFP-NEXT: sw a2, 8(s0)
+; RV32I-WITHFP-NEXT: addi a0, s0, 8
+; RV32I-WITHFP-NEXT: sw a0, -12(s0)
+; RV32I-WITHFP-NEXT: lw a0, 4(s0)
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 48
+; RV32I-WITHFP-NEXT: ret
%va = alloca i8*, align 4
%1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1)
@@ -48,23 +81,54 @@ define i32 @va1_va_arg(i8* %fmt, ...) no
; RV32I-LABEL: va1_va_arg:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: sw a1, 4(s0)
-; RV32I-NEXT: sw a7, 28(s0)
-; RV32I-NEXT: sw a6, 24(s0)
-; RV32I-NEXT: sw a5, 20(s0)
-; RV32I-NEXT: sw a4, 16(s0)
-; RV32I-NEXT: sw a3, 12(s0)
-; RV32I-NEXT: sw a2, 8(s0)
-; RV32I-NEXT: addi a0, s0, 8
-; RV32I-NEXT: sw a0, -12(s0)
-; RV32I-NEXT: lw a0, 4(s0)
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: sw a1, 20(sp)
+; RV32I-NEXT: sw a7, 44(sp)
+; RV32I-NEXT: sw a6, 40(sp)
+; RV32I-NEXT: sw a5, 36(sp)
+; RV32I-NEXT: sw a4, 32(sp)
+; RV32I-NEXT: sw a3, 28(sp)
+; RV32I-NEXT: sw a2, 24(sp)
+; RV32I-NEXT: addi a0, sp, 24
+; RV32I-NEXT: sw a0, 12(sp)
+; RV32I-NEXT: lw a0, 20(sp)
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: va1_va_arg:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -48
+; RV32I-FPELIM-NEXT: sw a1, 20(sp)
+; RV32I-FPELIM-NEXT: sw a7, 44(sp)
+; RV32I-FPELIM-NEXT: sw a6, 40(sp)
+; RV32I-FPELIM-NEXT: sw a5, 36(sp)
+; RV32I-FPELIM-NEXT: sw a4, 32(sp)
+; RV32I-FPELIM-NEXT: sw a3, 28(sp)
+; RV32I-FPELIM-NEXT: sw a2, 24(sp)
+; RV32I-FPELIM-NEXT: addi a0, sp, 24
+; RV32I-FPELIM-NEXT: sw a0, 12(sp)
+; RV32I-FPELIM-NEXT: lw a0, 20(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 48
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: va1_va_arg:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -48
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: sw a1, 4(s0)
+; RV32I-WITHFP-NEXT: sw a7, 28(s0)
+; RV32I-WITHFP-NEXT: sw a6, 24(s0)
+; RV32I-WITHFP-NEXT: sw a5, 20(s0)
+; RV32I-WITHFP-NEXT: sw a4, 16(s0)
+; RV32I-WITHFP-NEXT: sw a3, 12(s0)
+; RV32I-WITHFP-NEXT: sw a2, 8(s0)
+; RV32I-WITHFP-NEXT: addi a0, s0, 8
+; RV32I-WITHFP-NEXT: sw a0, -12(s0)
+; RV32I-WITHFP-NEXT: lw a0, 4(s0)
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 48
+; RV32I-WITHFP-NEXT: ret
%va = alloca i8*, align 4
%1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1)
@@ -107,6 +171,69 @@ define i32 @va1_va_arg_alloca(i8* %fmt,
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: va1_va_arg_alloca:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -48
+; RV32I-FPELIM-NEXT: sw ra, 12(sp)
+; RV32I-FPELIM-NEXT: sw s0, 8(sp)
+; RV32I-FPELIM-NEXT: sw s1, 4(sp)
+; RV32I-FPELIM-NEXT: addi s0, sp, 16
+; RV32I-FPELIM-NEXT: sw a1, 4(s0)
+; RV32I-FPELIM-NEXT: sw a7, 28(s0)
+; RV32I-FPELIM-NEXT: sw a6, 24(s0)
+; RV32I-FPELIM-NEXT: sw a5, 20(s0)
+; RV32I-FPELIM-NEXT: sw a4, 16(s0)
+; RV32I-FPELIM-NEXT: sw a3, 12(s0)
+; RV32I-FPELIM-NEXT: sw a2, 8(s0)
+; RV32I-FPELIM-NEXT: addi a0, s0, 8
+; RV32I-FPELIM-NEXT: sw a0, -16(s0)
+; RV32I-FPELIM-NEXT: lw s1, 4(s0)
+; RV32I-FPELIM-NEXT: addi a0, s1, 15
+; RV32I-FPELIM-NEXT: andi a0, a0, -16
+; RV32I-FPELIM-NEXT: sub a0, sp, a0
+; RV32I-FPELIM-NEXT: mv sp, a0
+; RV32I-FPELIM-NEXT: lui a1, %hi(notdead)
+; RV32I-FPELIM-NEXT: addi a1, a1, %lo(notdead)
+; RV32I-FPELIM-NEXT: jalr a1
+; RV32I-FPELIM-NEXT: mv a0, s1
+; RV32I-FPELIM-NEXT: addi sp, s0, -16
+; RV32I-FPELIM-NEXT: lw s1, 4(sp)
+; RV32I-FPELIM-NEXT: lw s0, 8(sp)
+; RV32I-FPELIM-NEXT: lw ra, 12(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 48
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: va1_va_arg_alloca:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -48
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: sw s1, 4(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: sw a1, 4(s0)
+; RV32I-WITHFP-NEXT: sw a7, 28(s0)
+; RV32I-WITHFP-NEXT: sw a6, 24(s0)
+; RV32I-WITHFP-NEXT: sw a5, 20(s0)
+; RV32I-WITHFP-NEXT: sw a4, 16(s0)
+; RV32I-WITHFP-NEXT: sw a3, 12(s0)
+; RV32I-WITHFP-NEXT: sw a2, 8(s0)
+; RV32I-WITHFP-NEXT: addi a0, s0, 8
+; RV32I-WITHFP-NEXT: sw a0, -16(s0)
+; RV32I-WITHFP-NEXT: lw s1, 4(s0)
+; RV32I-WITHFP-NEXT: addi a0, s1, 15
+; RV32I-WITHFP-NEXT: andi a0, a0, -16
+; RV32I-WITHFP-NEXT: sub a0, sp, a0
+; RV32I-WITHFP-NEXT: mv sp, a0
+; RV32I-WITHFP-NEXT: lui a1, %hi(notdead)
+; RV32I-WITHFP-NEXT: addi a1, a1, %lo(notdead)
+; RV32I-WITHFP-NEXT: jalr a1
+; RV32I-WITHFP-NEXT: mv a0, s1
+; RV32I-WITHFP-NEXT: addi sp, s0, -16
+; RV32I-WITHFP-NEXT: lw s1, 4(sp)
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 48
+; RV32I-WITHFP-NEXT: ret
%va = alloca i8*, align 4
%1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1)
@@ -122,8 +249,6 @@ define void @va1_caller() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, 261888
; RV32I-NEXT: mv a3, a0
; RV32I-NEXT: lui a0, %hi(va1)
@@ -131,11 +256,42 @@ define void @va1_caller() nounwind {
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: jalr a0
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; Pass a double, as a float would be promoted by a C/C++ frontend
+; RV32I-FPELIM-LABEL: va1_caller:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -16
+; RV32I-FPELIM-NEXT: sw ra, 12(sp)
+; RV32I-FPELIM-NEXT: lui a0, 261888
+; RV32I-FPELIM-NEXT: mv a3, a0
+; RV32I-FPELIM-NEXT: lui a0, %hi(va1)
+; RV32I-FPELIM-NEXT: addi a0, a0, %lo(va1)
+; RV32I-FPELIM-NEXT: addi a4, zero, 2
+; RV32I-FPELIM-NEXT: mv a2, zero
+; RV32I-FPELIM-NEXT: jalr a0
+; RV32I-FPELIM-NEXT: lw ra, 12(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 16
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: va1_caller:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -16
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: lui a0, 261888
+; RV32I-WITHFP-NEXT: mv a3, a0
+; RV32I-WITHFP-NEXT: lui a0, %hi(va1)
+; RV32I-WITHFP-NEXT: addi a0, a0, %lo(va1)
+; RV32I-WITHFP-NEXT: addi a4, zero, 2
+; RV32I-WITHFP-NEXT: mv a2, zero
+; RV32I-WITHFP-NEXT: jalr a0
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 16
+; RV32I-WITHFP-NEXT: ret
%1 = call i32 (i8*, ...) @va1(i8* undef, double 1.0, i32 2)
ret void
}
@@ -147,27 +303,66 @@ define double @va2(i8 *%fmt, ...) nounwi
; RV32I-LABEL: va2:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: sw a7, 28(s0)
-; RV32I-NEXT: sw a6, 24(s0)
-; RV32I-NEXT: sw a5, 20(s0)
-; RV32I-NEXT: sw a4, 16(s0)
-; RV32I-NEXT: sw a3, 12(s0)
-; RV32I-NEXT: sw a2, 8(s0)
-; RV32I-NEXT: sw a1, 4(s0)
-; RV32I-NEXT: addi a0, s0, 19
-; RV32I-NEXT: sw a0, -12(s0)
-; RV32I-NEXT: addi a0, s0, 11
+; RV32I-NEXT: sw a7, 44(sp)
+; RV32I-NEXT: sw a6, 40(sp)
+; RV32I-NEXT: sw a5, 36(sp)
+; RV32I-NEXT: sw a4, 32(sp)
+; RV32I-NEXT: sw a3, 28(sp)
+; RV32I-NEXT: sw a2, 24(sp)
+; RV32I-NEXT: sw a1, 20(sp)
+; RV32I-NEXT: addi a0, sp, 35
+; RV32I-NEXT: sw a0, 12(sp)
+; RV32I-NEXT: addi a0, sp, 27
; RV32I-NEXT: andi a1, a0, -8
; RV32I-NEXT: lw a0, 0(a1)
; RV32I-NEXT: ori a1, a1, 4
; RV32I-NEXT: lw a1, 0(a1)
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: va2:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -48
+; RV32I-FPELIM-NEXT: sw a7, 44(sp)
+; RV32I-FPELIM-NEXT: sw a6, 40(sp)
+; RV32I-FPELIM-NEXT: sw a5, 36(sp)
+; RV32I-FPELIM-NEXT: sw a4, 32(sp)
+; RV32I-FPELIM-NEXT: sw a3, 28(sp)
+; RV32I-FPELIM-NEXT: sw a2, 24(sp)
+; RV32I-FPELIM-NEXT: sw a1, 20(sp)
+; RV32I-FPELIM-NEXT: addi a0, sp, 35
+; RV32I-FPELIM-NEXT: sw a0, 12(sp)
+; RV32I-FPELIM-NEXT: addi a0, sp, 27
+; RV32I-FPELIM-NEXT: andi a1, a0, -8
+; RV32I-FPELIM-NEXT: lw a0, 0(a1)
+; RV32I-FPELIM-NEXT: ori a1, a1, 4
+; RV32I-FPELIM-NEXT: lw a1, 0(a1)
+; RV32I-FPELIM-NEXT: addi sp, sp, 48
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: va2:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -48
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: sw a7, 28(s0)
+; RV32I-WITHFP-NEXT: sw a6, 24(s0)
+; RV32I-WITHFP-NEXT: sw a5, 20(s0)
+; RV32I-WITHFP-NEXT: sw a4, 16(s0)
+; RV32I-WITHFP-NEXT: sw a3, 12(s0)
+; RV32I-WITHFP-NEXT: sw a2, 8(s0)
+; RV32I-WITHFP-NEXT: sw a1, 4(s0)
+; RV32I-WITHFP-NEXT: addi a0, s0, 19
+; RV32I-WITHFP-NEXT: sw a0, -12(s0)
+; RV32I-WITHFP-NEXT: addi a0, s0, 11
+; RV32I-WITHFP-NEXT: andi a1, a0, -8
+; RV32I-WITHFP-NEXT: lw a0, 0(a1)
+; RV32I-WITHFP-NEXT: ori a1, a1, 4
+; RV32I-WITHFP-NEXT: lw a1, 0(a1)
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 48
+; RV32I-WITHFP-NEXT: ret
%va = alloca i8*, align 4
%1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1)
@@ -188,28 +383,69 @@ define double @va2_va_arg(i8 *%fmt, ...)
; RV32I-LABEL: va2_va_arg:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: sw a7, 28(s0)
-; RV32I-NEXT: sw a6, 24(s0)
-; RV32I-NEXT: sw a5, 20(s0)
-; RV32I-NEXT: sw a4, 16(s0)
-; RV32I-NEXT: sw a3, 12(s0)
-; RV32I-NEXT: sw a2, 8(s0)
-; RV32I-NEXT: sw a1, 4(s0)
-; RV32I-NEXT: addi a0, s0, 11
+; RV32I-NEXT: sw a7, 44(sp)
+; RV32I-NEXT: sw a6, 40(sp)
+; RV32I-NEXT: sw a5, 36(sp)
+; RV32I-NEXT: sw a4, 32(sp)
+; RV32I-NEXT: sw a3, 28(sp)
+; RV32I-NEXT: sw a2, 24(sp)
+; RV32I-NEXT: sw a1, 20(sp)
+; RV32I-NEXT: addi a0, sp, 27
; RV32I-NEXT: andi a0, a0, -8
; RV32I-NEXT: ori a1, a0, 4
-; RV32I-NEXT: sw a1, -12(s0)
+; RV32I-NEXT: sw a1, 12(sp)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: addi a2, a1, 4
-; RV32I-NEXT: sw a2, -12(s0)
+; RV32I-NEXT: sw a2, 12(sp)
; RV32I-NEXT: lw a1, 0(a1)
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: va2_va_arg:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -48
+; RV32I-FPELIM-NEXT: sw a7, 44(sp)
+; RV32I-FPELIM-NEXT: sw a6, 40(sp)
+; RV32I-FPELIM-NEXT: sw a5, 36(sp)
+; RV32I-FPELIM-NEXT: sw a4, 32(sp)
+; RV32I-FPELIM-NEXT: sw a3, 28(sp)
+; RV32I-FPELIM-NEXT: sw a2, 24(sp)
+; RV32I-FPELIM-NEXT: sw a1, 20(sp)
+; RV32I-FPELIM-NEXT: addi a0, sp, 27
+; RV32I-FPELIM-NEXT: andi a0, a0, -8
+; RV32I-FPELIM-NEXT: ori a1, a0, 4
+; RV32I-FPELIM-NEXT: sw a1, 12(sp)
+; RV32I-FPELIM-NEXT: lw a0, 0(a0)
+; RV32I-FPELIM-NEXT: addi a2, a1, 4
+; RV32I-FPELIM-NEXT: sw a2, 12(sp)
+; RV32I-FPELIM-NEXT: lw a1, 0(a1)
+; RV32I-FPELIM-NEXT: addi sp, sp, 48
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: va2_va_arg:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -48
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: sw a7, 28(s0)
+; RV32I-WITHFP-NEXT: sw a6, 24(s0)
+; RV32I-WITHFP-NEXT: sw a5, 20(s0)
+; RV32I-WITHFP-NEXT: sw a4, 16(s0)
+; RV32I-WITHFP-NEXT: sw a3, 12(s0)
+; RV32I-WITHFP-NEXT: sw a2, 8(s0)
+; RV32I-WITHFP-NEXT: sw a1, 4(s0)
+; RV32I-WITHFP-NEXT: addi a0, s0, 11
+; RV32I-WITHFP-NEXT: andi a0, a0, -8
+; RV32I-WITHFP-NEXT: ori a1, a0, 4
+; RV32I-WITHFP-NEXT: sw a1, -12(s0)
+; RV32I-WITHFP-NEXT: lw a0, 0(a0)
+; RV32I-WITHFP-NEXT: addi a2, a1, 4
+; RV32I-WITHFP-NEXT: sw a2, -12(s0)
+; RV32I-WITHFP-NEXT: lw a1, 0(a1)
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 48
+; RV32I-WITHFP-NEXT: ret
%va = alloca i8*, align 4
%1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1)
@@ -223,18 +459,45 @@ define void @va2_caller() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, 261888
; RV32I-NEXT: mv a3, a0
; RV32I-NEXT: lui a0, %hi(va2)
; RV32I-NEXT: addi a0, a0, %lo(va2)
; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: jalr a0
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: va2_caller:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -16
+; RV32I-FPELIM-NEXT: sw ra, 12(sp)
+; RV32I-FPELIM-NEXT: lui a0, 261888
+; RV32I-FPELIM-NEXT: mv a3, a0
+; RV32I-FPELIM-NEXT: lui a0, %hi(va2)
+; RV32I-FPELIM-NEXT: addi a0, a0, %lo(va2)
+; RV32I-FPELIM-NEXT: mv a2, zero
+; RV32I-FPELIM-NEXT: jalr a0
+; RV32I-FPELIM-NEXT: lw ra, 12(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 16
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: va2_caller:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -16
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: lui a0, 261888
+; RV32I-WITHFP-NEXT: mv a3, a0
+; RV32I-WITHFP-NEXT: lui a0, %hi(va2)
+; RV32I-WITHFP-NEXT: addi a0, a0, %lo(va2)
+; RV32I-WITHFP-NEXT: mv a2, zero
+; RV32I-WITHFP-NEXT: jalr a0
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 16
+; RV32I-WITHFP-NEXT: ret
%1 = call double (i8*, ...) @va2(i8* undef, double 1.000000e+00)
ret void
}
@@ -245,20 +508,18 @@ define void @va2_caller() nounwind {
define double @va3(i32 %a, double %b, ...) nounwind {
; RV32I-LABEL: va3:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -48
-; RV32I-NEXT: sw ra, 20(sp)
-; RV32I-NEXT: sw s0, 16(sp)
-; RV32I-NEXT: addi s0, sp, 24
-; RV32I-NEXT: sw a7, 20(s0)
-; RV32I-NEXT: sw a6, 16(s0)
-; RV32I-NEXT: sw a5, 12(s0)
-; RV32I-NEXT: sw a4, 8(s0)
-; RV32I-NEXT: sw a3, 4(s0)
-; RV32I-NEXT: addi a0, s0, 19
-; RV32I-NEXT: sw a0, -12(s0)
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 4(sp)
+; RV32I-NEXT: sw a7, 28(sp)
+; RV32I-NEXT: sw a6, 24(sp)
+; RV32I-NEXT: sw a5, 20(sp)
+; RV32I-NEXT: sw a4, 16(sp)
+; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: addi a0, sp, 27
+; RV32I-NEXT: sw a0, 0(sp)
; RV32I-NEXT: lui a0, %hi(__adddf3)
; RV32I-NEXT: addi a5, a0, %lo(__adddf3)
-; RV32I-NEXT: addi a0, s0, 11
+; RV32I-NEXT: addi a0, sp, 19
; RV32I-NEXT: andi a0, a0, -8
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: ori a0, a0, 4
@@ -267,10 +528,63 @@ define double @va3(i32 %a, double %b, ..
; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: jalr a5
-; RV32I-NEXT: lw s0, 16(sp)
-; RV32I-NEXT: lw ra, 20(sp)
-; RV32I-NEXT: addi sp, sp, 48
+; RV32I-NEXT: lw ra, 4(sp)
+; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: va3:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -32
+; RV32I-FPELIM-NEXT: sw ra, 4(sp)
+; RV32I-FPELIM-NEXT: sw a7, 28(sp)
+; RV32I-FPELIM-NEXT: sw a6, 24(sp)
+; RV32I-FPELIM-NEXT: sw a5, 20(sp)
+; RV32I-FPELIM-NEXT: sw a4, 16(sp)
+; RV32I-FPELIM-NEXT: sw a3, 12(sp)
+; RV32I-FPELIM-NEXT: addi a0, sp, 27
+; RV32I-FPELIM-NEXT: sw a0, 0(sp)
+; RV32I-FPELIM-NEXT: lui a0, %hi(__adddf3)
+; RV32I-FPELIM-NEXT: addi a5, a0, %lo(__adddf3)
+; RV32I-FPELIM-NEXT: addi a0, sp, 19
+; RV32I-FPELIM-NEXT: andi a0, a0, -8
+; RV32I-FPELIM-NEXT: lw a4, 0(a0)
+; RV32I-FPELIM-NEXT: ori a0, a0, 4
+; RV32I-FPELIM-NEXT: lw a3, 0(a0)
+; RV32I-FPELIM-NEXT: mv a0, a1
+; RV32I-FPELIM-NEXT: mv a1, a2
+; RV32I-FPELIM-NEXT: mv a2, a4
+; RV32I-FPELIM-NEXT: jalr a5
+; RV32I-FPELIM-NEXT: lw ra, 4(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 32
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: va3:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -48
+; RV32I-WITHFP-NEXT: sw ra, 20(sp)
+; RV32I-WITHFP-NEXT: sw s0, 16(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 24
+; RV32I-WITHFP-NEXT: sw a7, 20(s0)
+; RV32I-WITHFP-NEXT: sw a6, 16(s0)
+; RV32I-WITHFP-NEXT: sw a5, 12(s0)
+; RV32I-WITHFP-NEXT: sw a4, 8(s0)
+; RV32I-WITHFP-NEXT: sw a3, 4(s0)
+; RV32I-WITHFP-NEXT: addi a0, s0, 19
+; RV32I-WITHFP-NEXT: sw a0, -12(s0)
+; RV32I-WITHFP-NEXT: lui a0, %hi(__adddf3)
+; RV32I-WITHFP-NEXT: addi a5, a0, %lo(__adddf3)
+; RV32I-WITHFP-NEXT: addi a0, s0, 11
+; RV32I-WITHFP-NEXT: andi a0, a0, -8
+; RV32I-WITHFP-NEXT: lw a4, 0(a0)
+; RV32I-WITHFP-NEXT: ori a0, a0, 4
+; RV32I-WITHFP-NEXT: lw a3, 0(a0)
+; RV32I-WITHFP-NEXT: mv a0, a1
+; RV32I-WITHFP-NEXT: mv a1, a2
+; RV32I-WITHFP-NEXT: mv a2, a4
+; RV32I-WITHFP-NEXT: jalr a5
+; RV32I-WITHFP-NEXT: lw s0, 16(sp)
+; RV32I-WITHFP-NEXT: lw ra, 20(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 48
+; RV32I-WITHFP-NEXT: ret
%va = alloca i8*, align 4
%1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1)
@@ -291,22 +605,20 @@ define double @va3(i32 %a, double %b, ..
define double @va3_va_arg(i32 %a, double %b, ...) nounwind {
; RV32I-LABEL: va3_va_arg:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -48
-; RV32I-NEXT: sw ra, 20(sp)
-; RV32I-NEXT: sw s0, 16(sp)
-; RV32I-NEXT: addi s0, sp, 24
-; RV32I-NEXT: sw a7, 20(s0)
-; RV32I-NEXT: sw a6, 16(s0)
-; RV32I-NEXT: sw a5, 12(s0)
-; RV32I-NEXT: sw a4, 8(s0)
-; RV32I-NEXT: sw a3, 4(s0)
-; RV32I-NEXT: addi a0, s0, 11
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 4(sp)
+; RV32I-NEXT: sw a7, 28(sp)
+; RV32I-NEXT: sw a6, 24(sp)
+; RV32I-NEXT: sw a5, 20(sp)
+; RV32I-NEXT: sw a4, 16(sp)
+; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: addi a0, sp, 19
; RV32I-NEXT: andi a0, a0, -8
; RV32I-NEXT: ori a3, a0, 4
-; RV32I-NEXT: sw a3, -12(s0)
+; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: addi a0, a3, 4
-; RV32I-NEXT: sw a0, -12(s0)
+; RV32I-NEXT: sw a0, 0(sp)
; RV32I-NEXT: lui a0, %hi(__adddf3)
; RV32I-NEXT: addi a5, a0, %lo(__adddf3)
; RV32I-NEXT: lw a3, 0(a3)
@@ -314,10 +626,65 @@ define double @va3_va_arg(i32 %a, double
; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: jalr a5
-; RV32I-NEXT: lw s0, 16(sp)
-; RV32I-NEXT: lw ra, 20(sp)
-; RV32I-NEXT: addi sp, sp, 48
+; RV32I-NEXT: lw ra, 4(sp)
+; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: va3_va_arg:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -32
+; RV32I-FPELIM-NEXT: sw ra, 4(sp)
+; RV32I-FPELIM-NEXT: sw a7, 28(sp)
+; RV32I-FPELIM-NEXT: sw a6, 24(sp)
+; RV32I-FPELIM-NEXT: sw a5, 20(sp)
+; RV32I-FPELIM-NEXT: sw a4, 16(sp)
+; RV32I-FPELIM-NEXT: sw a3, 12(sp)
+; RV32I-FPELIM-NEXT: addi a0, sp, 19
+; RV32I-FPELIM-NEXT: andi a0, a0, -8
+; RV32I-FPELIM-NEXT: ori a3, a0, 4
+; RV32I-FPELIM-NEXT: sw a3, 0(sp)
+; RV32I-FPELIM-NEXT: lw a4, 0(a0)
+; RV32I-FPELIM-NEXT: addi a0, a3, 4
+; RV32I-FPELIM-NEXT: sw a0, 0(sp)
+; RV32I-FPELIM-NEXT: lui a0, %hi(__adddf3)
+; RV32I-FPELIM-NEXT: addi a5, a0, %lo(__adddf3)
+; RV32I-FPELIM-NEXT: lw a3, 0(a3)
+; RV32I-FPELIM-NEXT: mv a0, a1
+; RV32I-FPELIM-NEXT: mv a1, a2
+; RV32I-FPELIM-NEXT: mv a2, a4
+; RV32I-FPELIM-NEXT: jalr a5
+; RV32I-FPELIM-NEXT: lw ra, 4(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 32
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: va3_va_arg:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -48
+; RV32I-WITHFP-NEXT: sw ra, 20(sp)
+; RV32I-WITHFP-NEXT: sw s0, 16(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 24
+; RV32I-WITHFP-NEXT: sw a7, 20(s0)
+; RV32I-WITHFP-NEXT: sw a6, 16(s0)
+; RV32I-WITHFP-NEXT: sw a5, 12(s0)
+; RV32I-WITHFP-NEXT: sw a4, 8(s0)
+; RV32I-WITHFP-NEXT: sw a3, 4(s0)
+; RV32I-WITHFP-NEXT: addi a0, s0, 11
+; RV32I-WITHFP-NEXT: andi a0, a0, -8
+; RV32I-WITHFP-NEXT: ori a3, a0, 4
+; RV32I-WITHFP-NEXT: sw a3, -12(s0)
+; RV32I-WITHFP-NEXT: lw a4, 0(a0)
+; RV32I-WITHFP-NEXT: addi a0, a3, 4
+; RV32I-WITHFP-NEXT: sw a0, -12(s0)
+; RV32I-WITHFP-NEXT: lui a0, %hi(__adddf3)
+; RV32I-WITHFP-NEXT: addi a5, a0, %lo(__adddf3)
+; RV32I-WITHFP-NEXT: lw a3, 0(a3)
+; RV32I-WITHFP-NEXT: mv a0, a1
+; RV32I-WITHFP-NEXT: mv a1, a2
+; RV32I-WITHFP-NEXT: mv a2, a4
+; RV32I-WITHFP-NEXT: jalr a5
+; RV32I-WITHFP-NEXT: lw s0, 16(sp)
+; RV32I-WITHFP-NEXT: lw ra, 20(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 48
+; RV32I-WITHFP-NEXT: ret
%va = alloca i8*, align 4
%1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1)
@@ -332,8 +699,6 @@ define void @va3_caller() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, 261888
; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: lui a0, 262144
@@ -344,10 +709,47 @@ define void @va3_caller() nounwind {
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: jalr a3
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: va3_caller:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -16
+; RV32I-FPELIM-NEXT: sw ra, 12(sp)
+; RV32I-FPELIM-NEXT: lui a0, 261888
+; RV32I-FPELIM-NEXT: mv a2, a0
+; RV32I-FPELIM-NEXT: lui a0, 262144
+; RV32I-FPELIM-NEXT: mv a5, a0
+; RV32I-FPELIM-NEXT: lui a0, %hi(va3)
+; RV32I-FPELIM-NEXT: addi a3, a0, %lo(va3)
+; RV32I-FPELIM-NEXT: addi a0, zero, 2
+; RV32I-FPELIM-NEXT: mv a1, zero
+; RV32I-FPELIM-NEXT: mv a4, zero
+; RV32I-FPELIM-NEXT: jalr a3
+; RV32I-FPELIM-NEXT: lw ra, 12(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 16
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: va3_caller:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -16
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: lui a0, 261888
+; RV32I-WITHFP-NEXT: mv a2, a0
+; RV32I-WITHFP-NEXT: lui a0, 262144
+; RV32I-WITHFP-NEXT: mv a5, a0
+; RV32I-WITHFP-NEXT: lui a0, %hi(va3)
+; RV32I-WITHFP-NEXT: addi a3, a0, %lo(va3)
+; RV32I-WITHFP-NEXT: addi a0, zero, 2
+; RV32I-WITHFP-NEXT: mv a1, zero
+; RV32I-WITHFP-NEXT: mv a4, zero
+; RV32I-WITHFP-NEXT: jalr a3
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 16
+; RV32I-WITHFP-NEXT: ret
%1 = call double (i32, double, ...) @va3(i32 2, double 1.000000e+00, double 2.000000e+00)
ret void
}
@@ -357,49 +759,134 @@ declare void @llvm.va_copy(i8*, i8*)
define i32 @va4_va_copy(i32 %argno, ...) nounwind {
; RV32I-LABEL: va4_va_copy:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -64
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: addi s0, sp, 32
-; RV32I-NEXT: sw a1, 4(s0)
-; RV32I-NEXT: sw a7, 28(s0)
-; RV32I-NEXT: sw a6, 24(s0)
-; RV32I-NEXT: sw a5, 20(s0)
-; RV32I-NEXT: sw a4, 16(s0)
-; RV32I-NEXT: sw a3, 12(s0)
-; RV32I-NEXT: sw a2, 8(s0)
-; RV32I-NEXT: addi a0, s0, 8
-; RV32I-NEXT: sw a0, -16(s0)
-; RV32I-NEXT: sw a0, -20(s0)
-; RV32I-NEXT: lw s1, 4(s0)
+; RV32I-NEXT: addi sp, sp, -48
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s1, 8(sp)
+; RV32I-NEXT: sw a1, 20(sp)
+; RV32I-NEXT: sw a7, 44(sp)
+; RV32I-NEXT: sw a6, 40(sp)
+; RV32I-NEXT: sw a5, 36(sp)
+; RV32I-NEXT: sw a4, 32(sp)
+; RV32I-NEXT: sw a3, 28(sp)
+; RV32I-NEXT: sw a2, 24(sp)
+; RV32I-NEXT: addi a0, sp, 24
+; RV32I-NEXT: sw a0, 4(sp)
+; RV32I-NEXT: sw a0, 0(sp)
+; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lui a1, %hi(notdead)
; RV32I-NEXT: addi a1, a1, %lo(notdead)
; RV32I-NEXT: jalr a1
-; RV32I-NEXT: lw a0, -16(s0)
+; RV32I-NEXT: lw a0, 4(sp)
; RV32I-NEXT: addi a0, a0, 3
; RV32I-NEXT: andi a0, a0, -4
; RV32I-NEXT: addi a1, a0, 4
-; RV32I-NEXT: sw a1, -16(s0)
+; RV32I-NEXT: sw a1, 4(sp)
; RV32I-NEXT: lw a1, 0(a0)
; RV32I-NEXT: addi a0, a0, 7
; RV32I-NEXT: andi a0, a0, -4
; RV32I-NEXT: addi a2, a0, 4
-; RV32I-NEXT: sw a2, -16(s0)
+; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: addi a0, a0, 7
; RV32I-NEXT: andi a0, a0, -4
; RV32I-NEXT: addi a3, a0, 4
-; RV32I-NEXT: sw a3, -16(s0)
+; RV32I-NEXT: sw a3, 4(sp)
; RV32I-NEXT: add a1, a1, s1
; RV32I-NEXT: add a1, a1, a2
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: add a0, a1, a0
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 64
+; RV32I-NEXT: lw s1, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: va4_va_copy:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -48
+; RV32I-FPELIM-NEXT: sw ra, 12(sp)
+; RV32I-FPELIM-NEXT: sw s1, 8(sp)
+; RV32I-FPELIM-NEXT: sw a1, 20(sp)
+; RV32I-FPELIM-NEXT: sw a7, 44(sp)
+; RV32I-FPELIM-NEXT: sw a6, 40(sp)
+; RV32I-FPELIM-NEXT: sw a5, 36(sp)
+; RV32I-FPELIM-NEXT: sw a4, 32(sp)
+; RV32I-FPELIM-NEXT: sw a3, 28(sp)
+; RV32I-FPELIM-NEXT: sw a2, 24(sp)
+; RV32I-FPELIM-NEXT: addi a0, sp, 24
+; RV32I-FPELIM-NEXT: sw a0, 4(sp)
+; RV32I-FPELIM-NEXT: sw a0, 0(sp)
+; RV32I-FPELIM-NEXT: lw s1, 20(sp)
+; RV32I-FPELIM-NEXT: lui a1, %hi(notdead)
+; RV32I-FPELIM-NEXT: addi a1, a1, %lo(notdead)
+; RV32I-FPELIM-NEXT: jalr a1
+; RV32I-FPELIM-NEXT: lw a0, 4(sp)
+; RV32I-FPELIM-NEXT: addi a0, a0, 3
+; RV32I-FPELIM-NEXT: andi a0, a0, -4
+; RV32I-FPELIM-NEXT: addi a1, a0, 4
+; RV32I-FPELIM-NEXT: sw a1, 4(sp)
+; RV32I-FPELIM-NEXT: lw a1, 0(a0)
+; RV32I-FPELIM-NEXT: addi a0, a0, 7
+; RV32I-FPELIM-NEXT: andi a0, a0, -4
+; RV32I-FPELIM-NEXT: addi a2, a0, 4
+; RV32I-FPELIM-NEXT: sw a2, 4(sp)
+; RV32I-FPELIM-NEXT: lw a2, 0(a0)
+; RV32I-FPELIM-NEXT: addi a0, a0, 7
+; RV32I-FPELIM-NEXT: andi a0, a0, -4
+; RV32I-FPELIM-NEXT: addi a3, a0, 4
+; RV32I-FPELIM-NEXT: sw a3, 4(sp)
+; RV32I-FPELIM-NEXT: add a1, a1, s1
+; RV32I-FPELIM-NEXT: add a1, a1, a2
+; RV32I-FPELIM-NEXT: lw a0, 0(a0)
+; RV32I-FPELIM-NEXT: add a0, a1, a0
+; RV32I-FPELIM-NEXT: lw s1, 8(sp)
+; RV32I-FPELIM-NEXT: lw ra, 12(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 48
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: va4_va_copy:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -64
+; RV32I-WITHFP-NEXT: sw ra, 28(sp)
+; RV32I-WITHFP-NEXT: sw s0, 24(sp)
+; RV32I-WITHFP-NEXT: sw s1, 20(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 32
+; RV32I-WITHFP-NEXT: sw a1, 4(s0)
+; RV32I-WITHFP-NEXT: sw a7, 28(s0)
+; RV32I-WITHFP-NEXT: sw a6, 24(s0)
+; RV32I-WITHFP-NEXT: sw a5, 20(s0)
+; RV32I-WITHFP-NEXT: sw a4, 16(s0)
+; RV32I-WITHFP-NEXT: sw a3, 12(s0)
+; RV32I-WITHFP-NEXT: sw a2, 8(s0)
+; RV32I-WITHFP-NEXT: addi a0, s0, 8
+; RV32I-WITHFP-NEXT: sw a0, -16(s0)
+; RV32I-WITHFP-NEXT: sw a0, -20(s0)
+; RV32I-WITHFP-NEXT: lw s1, 4(s0)
+; RV32I-WITHFP-NEXT: lui a1, %hi(notdead)
+; RV32I-WITHFP-NEXT: addi a1, a1, %lo(notdead)
+; RV32I-WITHFP-NEXT: jalr a1
+; RV32I-WITHFP-NEXT: lw a0, -16(s0)
+; RV32I-WITHFP-NEXT: addi a0, a0, 3
+; RV32I-WITHFP-NEXT: andi a0, a0, -4
+; RV32I-WITHFP-NEXT: addi a1, a0, 4
+; RV32I-WITHFP-NEXT: sw a1, -16(s0)
+; RV32I-WITHFP-NEXT: lw a1, 0(a0)
+; RV32I-WITHFP-NEXT: addi a0, a0, 7
+; RV32I-WITHFP-NEXT: andi a0, a0, -4
+; RV32I-WITHFP-NEXT: addi a2, a0, 4
+; RV32I-WITHFP-NEXT: sw a2, -16(s0)
+; RV32I-WITHFP-NEXT: lw a2, 0(a0)
+; RV32I-WITHFP-NEXT: addi a0, a0, 7
+; RV32I-WITHFP-NEXT: andi a0, a0, -4
+; RV32I-WITHFP-NEXT: addi a3, a0, 4
+; RV32I-WITHFP-NEXT: sw a3, -16(s0)
+; RV32I-WITHFP-NEXT: add a1, a1, s1
+; RV32I-WITHFP-NEXT: add a1, a1, a2
+; RV32I-WITHFP-NEXT: lw a0, 0(a0)
+; RV32I-WITHFP-NEXT: add a0, a1, a0
+; RV32I-WITHFP-NEXT: lw s1, 20(sp)
+; RV32I-WITHFP-NEXT: lw s0, 24(sp)
+; RV32I-WITHFP-NEXT: lw ra, 28(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 64
+; RV32I-WITHFP-NEXT: ret
%vargs = alloca i8*, align 4
%wargs = alloca i8*, align 4
%1 = bitcast i8** %vargs to i8*
@@ -425,22 +912,49 @@ define i32 @va4_va_copy(i32 %argno, ...)
define i32 @va5_aligned_stack_callee(i32 %a, ...) nounwind {
; RV32I-LABEL: va5_aligned_stack_callee:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -48
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: sw a7, 28(s0)
-; RV32I-NEXT: sw a6, 24(s0)
-; RV32I-NEXT: sw a5, 20(s0)
-; RV32I-NEXT: sw a4, 16(s0)
-; RV32I-NEXT: sw a3, 12(s0)
-; RV32I-NEXT: sw a2, 8(s0)
-; RV32I-NEXT: sw a1, 4(s0)
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw a7, 28(sp)
+; RV32I-NEXT: sw a6, 24(sp)
+; RV32I-NEXT: sw a5, 20(sp)
+; RV32I-NEXT: sw a4, 16(sp)
+; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: sw a2, 8(sp)
+; RV32I-NEXT: sw a1, 4(sp)
; RV32I-NEXT: addi a0, zero, 1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 48
+; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: va5_aligned_stack_callee:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -32
+; RV32I-FPELIM-NEXT: sw a7, 28(sp)
+; RV32I-FPELIM-NEXT: sw a6, 24(sp)
+; RV32I-FPELIM-NEXT: sw a5, 20(sp)
+; RV32I-FPELIM-NEXT: sw a4, 16(sp)
+; RV32I-FPELIM-NEXT: sw a3, 12(sp)
+; RV32I-FPELIM-NEXT: sw a2, 8(sp)
+; RV32I-FPELIM-NEXT: sw a1, 4(sp)
+; RV32I-FPELIM-NEXT: addi a0, zero, 1
+; RV32I-FPELIM-NEXT: addi sp, sp, 32
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: va5_aligned_stack_callee:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -48
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: sw a7, 28(s0)
+; RV32I-WITHFP-NEXT: sw a6, 24(s0)
+; RV32I-WITHFP-NEXT: sw a5, 20(s0)
+; RV32I-WITHFP-NEXT: sw a4, 16(s0)
+; RV32I-WITHFP-NEXT: sw a3, 12(s0)
+; RV32I-WITHFP-NEXT: sw a2, 8(s0)
+; RV32I-WITHFP-NEXT: sw a1, 4(s0)
+; RV32I-WITHFP-NEXT: addi a0, zero, 1
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 48
+; RV32I-WITHFP-NEXT: ret
ret i32 1
}
@@ -451,8 +965,6 @@ define void @va5_aligned_stack_caller()
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -64
; RV32I-NEXT: sw ra, 60(sp)
-; RV32I-NEXT: sw s0, 56(sp)
-; RV32I-NEXT: addi s0, sp, 64
; RV32I-NEXT: addi a0, zero, 17
; RV32I-NEXT: sw a0, 24(sp)
; RV32I-NEXT: addi a0, zero, 16
@@ -469,31 +981,122 @@ define void @va5_aligned_stack_caller()
; RV32I-NEXT: sw a0, 0(sp)
; RV32I-NEXT: lui a0, 262153
; RV32I-NEXT: addi a0, a0, 491
-; RV32I-NEXT: sw a0, -20(s0)
+; RV32I-NEXT: sw a0, 44(sp)
; RV32I-NEXT: lui a0, 545260
; RV32I-NEXT: addi a0, a0, -1967
-; RV32I-NEXT: sw a0, -24(s0)
+; RV32I-NEXT: sw a0, 40(sp)
; RV32I-NEXT: lui a0, 964690
; RV32I-NEXT: addi a0, a0, -328
-; RV32I-NEXT: sw a0, -28(s0)
+; RV32I-NEXT: sw a0, 36(sp)
; RV32I-NEXT: lui a0, 335544
; RV32I-NEXT: addi a0, a0, 1311
-; RV32I-NEXT: sw a0, -32(s0)
+; RV32I-NEXT: sw a0, 32(sp)
; RV32I-NEXT: lui a0, 688509
; RV32I-NEXT: addi a6, a0, -2048
; RV32I-NEXT: lui a0, %hi(va5_aligned_stack_callee)
; RV32I-NEXT: addi a5, a0, %lo(va5_aligned_stack_callee)
; RV32I-NEXT: addi a0, zero, 1
; RV32I-NEXT: addi a1, zero, 11
-; RV32I-NEXT: addi a2, s0, -32
+; RV32I-NEXT: addi a2, sp, 32
; RV32I-NEXT: addi a3, zero, 12
; RV32I-NEXT: addi a4, zero, 13
; RV32I-NEXT: addi a7, zero, 4
; RV32I-NEXT: jalr a5
-; RV32I-NEXT: lw s0, 56(sp)
; RV32I-NEXT: lw ra, 60(sp)
; RV32I-NEXT: addi sp, sp, 64
; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: va5_aligned_stack_caller:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -64
+; RV32I-FPELIM-NEXT: sw ra, 60(sp)
+; RV32I-FPELIM-NEXT: addi a0, zero, 17
+; RV32I-FPELIM-NEXT: sw a0, 24(sp)
+; RV32I-FPELIM-NEXT: addi a0, zero, 16
+; RV32I-FPELIM-NEXT: sw a0, 20(sp)
+; RV32I-FPELIM-NEXT: addi a0, zero, 15
+; RV32I-FPELIM-NEXT: sw a0, 16(sp)
+; RV32I-FPELIM-NEXT: lui a0, 262236
+; RV32I-FPELIM-NEXT: addi a0, a0, 655
+; RV32I-FPELIM-NEXT: sw a0, 12(sp)
+; RV32I-FPELIM-NEXT: lui a0, 377487
+; RV32I-FPELIM-NEXT: addi a0, a0, 1475
+; RV32I-FPELIM-NEXT: sw a0, 8(sp)
+; RV32I-FPELIM-NEXT: addi a0, zero, 14
+; RV32I-FPELIM-NEXT: sw a0, 0(sp)
+; RV32I-FPELIM-NEXT: lui a0, 262153
+; RV32I-FPELIM-NEXT: addi a0, a0, 491
+; RV32I-FPELIM-NEXT: sw a0, 44(sp)
+; RV32I-FPELIM-NEXT: lui a0, 545260
+; RV32I-FPELIM-NEXT: addi a0, a0, -1967
+; RV32I-FPELIM-NEXT: sw a0, 40(sp)
+; RV32I-FPELIM-NEXT: lui a0, 964690
+; RV32I-FPELIM-NEXT: addi a0, a0, -328
+; RV32I-FPELIM-NEXT: sw a0, 36(sp)
+; RV32I-FPELIM-NEXT: lui a0, 335544
+; RV32I-FPELIM-NEXT: addi a0, a0, 1311
+; RV32I-FPELIM-NEXT: sw a0, 32(sp)
+; RV32I-FPELIM-NEXT: lui a0, 688509
+; RV32I-FPELIM-NEXT: addi a6, a0, -2048
+; RV32I-FPELIM-NEXT: lui a0, %hi(va5_aligned_stack_callee)
+; RV32I-FPELIM-NEXT: addi a5, a0, %lo(va5_aligned_stack_callee)
+; RV32I-FPELIM-NEXT: addi a0, zero, 1
+; RV32I-FPELIM-NEXT: addi a1, zero, 11
+; RV32I-FPELIM-NEXT: addi a2, sp, 32
+; RV32I-FPELIM-NEXT: addi a3, zero, 12
+; RV32I-FPELIM-NEXT: addi a4, zero, 13
+; RV32I-FPELIM-NEXT: addi a7, zero, 4
+; RV32I-FPELIM-NEXT: jalr a5
+; RV32I-FPELIM-NEXT: lw ra, 60(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 64
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: va5_aligned_stack_caller:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -64
+; RV32I-WITHFP-NEXT: sw ra, 60(sp)
+; RV32I-WITHFP-NEXT: sw s0, 56(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 64
+; RV32I-WITHFP-NEXT: addi a0, zero, 17
+; RV32I-WITHFP-NEXT: sw a0, 24(sp)
+; RV32I-WITHFP-NEXT: addi a0, zero, 16
+; RV32I-WITHFP-NEXT: sw a0, 20(sp)
+; RV32I-WITHFP-NEXT: addi a0, zero, 15
+; RV32I-WITHFP-NEXT: sw a0, 16(sp)
+; RV32I-WITHFP-NEXT: lui a0, 262236
+; RV32I-WITHFP-NEXT: addi a0, a0, 655
+; RV32I-WITHFP-NEXT: sw a0, 12(sp)
+; RV32I-WITHFP-NEXT: lui a0, 377487
+; RV32I-WITHFP-NEXT: addi a0, a0, 1475
+; RV32I-WITHFP-NEXT: sw a0, 8(sp)
+; RV32I-WITHFP-NEXT: addi a0, zero, 14
+; RV32I-WITHFP-NEXT: sw a0, 0(sp)
+; RV32I-WITHFP-NEXT: lui a0, 262153
+; RV32I-WITHFP-NEXT: addi a0, a0, 491
+; RV32I-WITHFP-NEXT: sw a0, -20(s0)
+; RV32I-WITHFP-NEXT: lui a0, 545260
+; RV32I-WITHFP-NEXT: addi a0, a0, -1967
+; RV32I-WITHFP-NEXT: sw a0, -24(s0)
+; RV32I-WITHFP-NEXT: lui a0, 964690
+; RV32I-WITHFP-NEXT: addi a0, a0, -328
+; RV32I-WITHFP-NEXT: sw a0, -28(s0)
+; RV32I-WITHFP-NEXT: lui a0, 335544
+; RV32I-WITHFP-NEXT: addi a0, a0, 1311
+; RV32I-WITHFP-NEXT: sw a0, -32(s0)
+; RV32I-WITHFP-NEXT: lui a0, 688509
+; RV32I-WITHFP-NEXT: addi a6, a0, -2048
+; RV32I-WITHFP-NEXT: lui a0, %hi(va5_aligned_stack_callee)
+; RV32I-WITHFP-NEXT: addi a5, a0, %lo(va5_aligned_stack_callee)
+; RV32I-WITHFP-NEXT: addi a0, zero, 1
+; RV32I-WITHFP-NEXT: addi a1, zero, 11
+; RV32I-WITHFP-NEXT: addi a2, s0, -32
+; RV32I-WITHFP-NEXT: addi a3, zero, 12
+; RV32I-WITHFP-NEXT: addi a4, zero, 13
+; RV32I-WITHFP-NEXT: addi a7, zero, 4
+; RV32I-WITHFP-NEXT: jalr a5
+; RV32I-WITHFP-NEXT: lw s0, 56(sp)
+; RV32I-WITHFP-NEXT: lw ra, 60(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 64
+; RV32I-WITHFP-NEXT: ret
%1 = call i32 (i32, ...) @va5_aligned_stack_callee(i32 1, i32 11,
fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13, i64 20000000000,
i32 14, double 2.720000e+00, i32 15, [2 x i32] [i32 16, i32 17])
@@ -508,24 +1111,57 @@ define i32 @va6_no_fixed_args(...) nounw
; RV32I-LABEL: va6_no_fixed_args:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: sw a0, 0(s0)
-; RV32I-NEXT: sw a7, 28(s0)
-; RV32I-NEXT: sw a6, 24(s0)
-; RV32I-NEXT: sw a5, 20(s0)
-; RV32I-NEXT: sw a4, 16(s0)
-; RV32I-NEXT: sw a3, 12(s0)
-; RV32I-NEXT: sw a2, 8(s0)
-; RV32I-NEXT: sw a1, 4(s0)
-; RV32I-NEXT: addi a0, s0, 4
-; RV32I-NEXT: sw a0, -12(s0)
-; RV32I-NEXT: lw a0, 0(s0)
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: sw a0, 16(sp)
+; RV32I-NEXT: sw a7, 44(sp)
+; RV32I-NEXT: sw a6, 40(sp)
+; RV32I-NEXT: sw a5, 36(sp)
+; RV32I-NEXT: sw a4, 32(sp)
+; RV32I-NEXT: sw a3, 28(sp)
+; RV32I-NEXT: sw a2, 24(sp)
+; RV32I-NEXT: sw a1, 20(sp)
+; RV32I-NEXT: addi a0, sp, 20
+; RV32I-NEXT: sw a0, 12(sp)
+; RV32I-NEXT: lw a0, 16(sp)
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret
+; RV32I-FPELIM-LABEL: va6_no_fixed_args:
+; RV32I-FPELIM: # %bb.0:
+; RV32I-FPELIM-NEXT: addi sp, sp, -48
+; RV32I-FPELIM-NEXT: sw a0, 16(sp)
+; RV32I-FPELIM-NEXT: sw a7, 44(sp)
+; RV32I-FPELIM-NEXT: sw a6, 40(sp)
+; RV32I-FPELIM-NEXT: sw a5, 36(sp)
+; RV32I-FPELIM-NEXT: sw a4, 32(sp)
+; RV32I-FPELIM-NEXT: sw a3, 28(sp)
+; RV32I-FPELIM-NEXT: sw a2, 24(sp)
+; RV32I-FPELIM-NEXT: sw a1, 20(sp)
+; RV32I-FPELIM-NEXT: addi a0, sp, 20
+; RV32I-FPELIM-NEXT: sw a0, 12(sp)
+; RV32I-FPELIM-NEXT: lw a0, 16(sp)
+; RV32I-FPELIM-NEXT: addi sp, sp, 48
+; RV32I-FPELIM-NEXT: ret
+;
+; RV32I-WITHFP-LABEL: va6_no_fixed_args:
+; RV32I-WITHFP: # %bb.0:
+; RV32I-WITHFP-NEXT: addi sp, sp, -48
+; RV32I-WITHFP-NEXT: sw ra, 12(sp)
+; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: addi s0, sp, 16
+; RV32I-WITHFP-NEXT: sw a0, 0(s0)
+; RV32I-WITHFP-NEXT: sw a7, 28(s0)
+; RV32I-WITHFP-NEXT: sw a6, 24(s0)
+; RV32I-WITHFP-NEXT: sw a5, 20(s0)
+; RV32I-WITHFP-NEXT: sw a4, 16(s0)
+; RV32I-WITHFP-NEXT: sw a3, 12(s0)
+; RV32I-WITHFP-NEXT: sw a2, 8(s0)
+; RV32I-WITHFP-NEXT: sw a1, 4(s0)
+; RV32I-WITHFP-NEXT: addi a0, s0, 4
+; RV32I-WITHFP-NEXT: sw a0, -12(s0)
+; RV32I-WITHFP-NEXT: lw a0, 0(s0)
+; RV32I-WITHFP-NEXT: lw s0, 8(sp)
+; RV32I-WITHFP-NEXT: lw ra, 12(sp)
+; RV32I-WITHFP-NEXT: addi sp, sp, 48
+; RV32I-WITHFP-NEXT: ret
%va = alloca i8*, align 4
%1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1)
Modified: llvm/trunk/test/CodeGen/RISCV/wide-mem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/wide-mem.ll?rev=322839&r1=322838&r2=322839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/wide-mem.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/wide-mem.ll Thu Jan 18 03:34:02 2018
@@ -7,16 +7,9 @@
define i64 @load_i64(i64 *%a) nounwind {
; RV32I-LABEL: load_i64:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: mv a0, a2
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = load i64, i64* %a
ret i64 %1
@@ -29,19 +22,12 @@ define i64 @load_i64(i64 *%a) nounwind {
define i64 @load_i64_global() nounwind {
; RV32I-LABEL: load_i64_global:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, %hi(val64)
; RV32I-NEXT: addi a0, a0, %lo(val64)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: lui a1, %hi(val64+4)
; RV32I-NEXT: addi a1, a1, %lo(val64+4)
; RV32I-NEXT: lw a1, 0(a1)
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = load i64, i64* @val64
ret i64 %1
More information about the llvm-commits
mailing list