[PATCH] D42235: [AArch64] Avoid unnecessary vector byte-swapping in big-endian

[Pablo Barrio via Phabricator via llvm-commits]

pbarrio created this revision.
pbarrio added reviewers: olista01, SjoerdMeijer, efriedma.
Herald added subscribers: kristof.beyls, javed.absar, rengolin, aemerson.

Loads/stores of some NEON vector types are promoted to other vector
types with different lane sizes but same vector size. This is not a
problem in little-endian but, when in big-endian, it requires
additional byte reversals required to preserve the lane ordering
while keeping the right endianness of the data inside each lane.
For example:

%1 = load <4 x half>, <4 x half>* %p

results in the following assembly:

ld1 { v0.2s }, [x1]
rev32 v0.4h, v0.4h

This patch changes the promotion of these loads/stores so that the
actual vector load/store (LD1/ST1) takes care of the endianness
correctly and there is no need for further byte reversals. The
previous code now results in the following assembly:

ld1 { v0.4h }, [x1]


Repository:
  rL LLVM

https://reviews.llvm.org/D42235

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll

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