[llvm] r322820 - [X86] Use vmovdqu64/vmovdqa64 for unmasked integer vector stores for consistency with loads.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 17 23:44:09 PST 2018
Author: ctopper
Date: Wed Jan 17 23:44:09 2018
New Revision: 322820
URL: http://llvm.org/viewvc/llvm-project?rev=322820&view=rev
Log:
[X86] Use vmovdqu64/vmovdqa64 for unmasked integer vector stores for consistency with loads.
Previously we used 64 for vXi64 stores and 32 for everything else. This change uses 64 for everything just like do for loads.
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/lib/Target/X86/X86InstrVecCompiler.td
llvm/trunk/test/CodeGen/X86/avg.ll
llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll
llvm/trunk/test/CodeGen/X86/avx512-insert-extract_i1.ll
llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
llvm/trunk/test/CodeGen/X86/pr34605.ll
llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll
llvm/trunk/test/Transforms/LoopVectorize/X86/avx512.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=322820&r1=322819&r2=322820&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Wed Jan 17 23:44:09 2018
@@ -3287,7 +3287,7 @@ multiclass avx512_store_vl< bits<8> opc,
multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
AVX512VLVectorVTInfo _, Predicate prd,
- string Name> {
+ string Name, bit NoMRPattern = 0> {
let Predicates = [prd] in
defm Z : avx512_store<opc, OpcodeStr, SSE_MOVA, _.info512, alignedstore,
masked_store_aligned512, Name#Z>, EVEX_V512;
@@ -3327,7 +3327,7 @@ defm VMOVUPD : avx512_load_vl<0x10, "vmo
defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
HasAVX512, 1>,
avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
- HasAVX512, "VMOVDQA32">,
+ HasAVX512, "VMOVDQA32", 1>,
PD, EVEX_CD8<32, CD8VF>;
defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
@@ -3349,7 +3349,7 @@ defm VMOVDQU16 : avx512_load_vl<0x6F, "v
defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512,
1, null_frag>,
avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
- HasAVX512, "VMOVDQU32">,
+ HasAVX512, "VMOVDQU32", 1>,
XS, EVEX_CD8<32, CD8VF>;
defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512,
@@ -3451,35 +3451,41 @@ let Predicates = [HasBWI, NoVLX] in {
let Predicates = [HasAVX512] in {
// 512-bit store.
def : Pat<(alignedstore (v32i16 VR512:$src), addr:$dst),
- (VMOVDQA32Zmr addr:$dst, VR512:$src)>;
+ (VMOVDQA64Zmr addr:$dst, VR512:$src)>;
def : Pat<(alignedstore (v64i8 VR512:$src), addr:$dst),
- (VMOVDQA32Zmr addr:$dst, VR512:$src)>;
+ (VMOVDQA64Zmr addr:$dst, VR512:$src)>;
+ def : Pat<(store (v16i32 VR512:$src), addr:$dst),
+ (VMOVDQU64Zmr addr:$dst, VR512:$src)>;
def : Pat<(store (v32i16 VR512:$src), addr:$dst),
- (VMOVDQU32Zmr addr:$dst, VR512:$src)>;
+ (VMOVDQU64Zmr addr:$dst, VR512:$src)>;
def : Pat<(store (v64i8 VR512:$src), addr:$dst),
- (VMOVDQU32Zmr addr:$dst, VR512:$src)>;
+ (VMOVDQU64Zmr addr:$dst, VR512:$src)>;
}
let Predicates = [HasVLX] in {
// 128-bit store.
def : Pat<(alignedstore (v8i16 VR128X:$src), addr:$dst),
- (VMOVDQA32Z128mr addr:$dst, VR128X:$src)>;
+ (VMOVDQA64Z128mr addr:$dst, VR128X:$src)>;
def : Pat<(alignedstore (v16i8 VR128X:$src), addr:$dst),
- (VMOVDQA32Z128mr addr:$dst, VR128X:$src)>;
+ (VMOVDQA64Z128mr addr:$dst, VR128X:$src)>;
+ def : Pat<(store (v4i32 VR128X:$src), addr:$dst),
+ (VMOVDQU64Z128mr addr:$dst, VR128X:$src)>;
def : Pat<(store (v8i16 VR128X:$src), addr:$dst),
- (VMOVDQU32Z128mr addr:$dst, VR128X:$src)>;
+ (VMOVDQU64Z128mr addr:$dst, VR128X:$src)>;
def : Pat<(store (v16i8 VR128X:$src), addr:$dst),
- (VMOVDQU32Z128mr addr:$dst, VR128X:$src)>;
+ (VMOVDQU64Z128mr addr:$dst, VR128X:$src)>;
// 256-bit store.
def : Pat<(alignedstore (v16i16 VR256X:$src), addr:$dst),
- (VMOVDQA32Z256mr addr:$dst, VR256X:$src)>;
+ (VMOVDQA64Z256mr addr:$dst, VR256X:$src)>;
def : Pat<(alignedstore (v32i8 VR256X:$src), addr:$dst),
- (VMOVDQA32Z256mr addr:$dst, VR256X:$src)>;
+ (VMOVDQA64Z256mr addr:$dst, VR256X:$src)>;
+ def : Pat<(store (v8i32 VR256X:$src), addr:$dst),
+ (VMOVDQU64Z256mr addr:$dst, VR256X:$src)>;
def : Pat<(store (v16i16 VR256X:$src), addr:$dst),
- (VMOVDQU32Z256mr addr:$dst, VR256X:$src)>;
+ (VMOVDQU64Z256mr addr:$dst, VR256X:$src)>;
def : Pat<(store (v32i8 VR256X:$src), addr:$dst),
- (VMOVDQU32Z256mr addr:$dst, VR256X:$src)>;
+ (VMOVDQU64Z256mr addr:$dst, VR256X:$src)>;
}
multiclass masked_move_for_extract<string InstrStr, X86VectorVTInfo From,
Modified: llvm/trunk/lib/Target/X86/X86InstrVecCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrVecCompiler.td?rev=322820&r1=322819&r2=322820&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrVecCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrVecCompiler.td Wed Jan 17 23:44:09 2018
@@ -217,13 +217,13 @@ let Predicates = [HasVLX] in {
sub_xmm>;
defm : subvector_store_lowering<"APSZ128", "UPSZ128", VR256X, v4f32, v8f32,
sub_xmm>;
- defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR256X, v2i64,
+ defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR256X, v2i64,
v4i64, sub_xmm>;
- defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR256X, v4i32,
+ defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR256X, v4i32,
v8i32, sub_xmm>;
- defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR256X, v8i16,
+ defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR256X, v8i16,
v16i16, sub_xmm>;
- defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR256X, v16i8,
+ defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR256X, v16i8,
v32i8, sub_xmm>;
// Special patterns for storing subvector extracts of lower 128-bits of 512.
@@ -232,13 +232,13 @@ let Predicates = [HasVLX] in {
sub_xmm>;
defm : subvector_store_lowering<"APSZ128", "UPSZ128", VR512, v4f32, v16f32,
sub_xmm>;
- defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR512, v2i64,
+ defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR512, v2i64,
v8i64, sub_xmm>;
- defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR512, v4i32,
+ defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR512, v4i32,
v16i32, sub_xmm>;
- defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR512, v8i16,
+ defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR512, v8i16,
v32i16, sub_xmm>;
- defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR512, v16i8,
+ defm : subvector_store_lowering<"DQA64Z128", "DQU64Z128", VR512, v16i8,
v64i8, sub_xmm>;
// Special patterns for storing subvector extracts of lower 256-bits of 512.
@@ -247,13 +247,13 @@ let Predicates = [HasVLX] in {
sub_ymm>;
defm : subvector_store_lowering<"APSZ256", "UPSZ256", VR512, v8f32, v16f32,
sub_ymm>;
- defm : subvector_store_lowering<"DQA32Z256", "DQU32Z256", VR512, v4i64,
+ defm : subvector_store_lowering<"DQA64Z256", "DQU64Z256", VR512, v4i64,
v8i64, sub_ymm>;
- defm : subvector_store_lowering<"DQA32Z256", "DQU32Z256", VR512, v8i32,
+ defm : subvector_store_lowering<"DQA64Z256", "DQU64Z256", VR512, v8i32,
v16i32, sub_ymm>;
- defm : subvector_store_lowering<"DQA32Z256", "DQU32Z256", VR512, v16i16,
+ defm : subvector_store_lowering<"DQA64Z256", "DQU64Z256", VR512, v16i16,
v32i16, sub_ymm>;
- defm : subvector_store_lowering<"DQA32Z256", "DQU32Z256", VR512, v32i8,
+ defm : subvector_store_lowering<"DQA64Z256", "DQU64Z256", VR512, v32i8,
v64i8, sub_ymm>;
}
Modified: llvm/trunk/test/CodeGen/X86/avg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avg.ll?rev=322820&r1=322819&r2=322820&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avg.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avg.ll Wed Jan 17 23:44:09 2018
@@ -606,7 +606,7 @@ define void @avg_v64i8(<64 x i8>* %a, <6
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovdqa64 (%rsi), %zmm0
; AVX512BW-NEXT: vpavgb (%rdi), %zmm0, %zmm0
-; AVX512BW-NEXT: vmovdqu32 %zmm0, (%rax)
+; AVX512BW-NEXT: vmovdqu64 %zmm0, (%rax)
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%1 = load <64 x i8>, <64 x i8>* %a
@@ -790,7 +790,7 @@ define void @avg_v32i16(<32 x i16>* %a,
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovdqa64 (%rsi), %zmm0
; AVX512BW-NEXT: vpavgw (%rdi), %zmm0, %zmm0
-; AVX512BW-NEXT: vmovdqu32 %zmm0, (%rax)
+; AVX512BW-NEXT: vmovdqu64 %zmm0, (%rax)
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%1 = load <32 x i16>, <32 x i16>* %a
@@ -998,7 +998,7 @@ define void @avg_v64i8_2(<64 x i8>* %a,
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovdqa64 (%rsi), %zmm0
; AVX512BW-NEXT: vpavgb %zmm0, %zmm0, %zmm0
-; AVX512BW-NEXT: vmovdqu32 %zmm0, (%rax)
+; AVX512BW-NEXT: vmovdqu64 %zmm0, (%rax)
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%1 = load <64 x i8>, <64 x i8>* %a
@@ -1183,7 +1183,7 @@ define void @avg_v32i16_2(<32 x i16>* %a
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm0
; AVX512BW-NEXT: vpavgw (%rsi), %zmm0, %zmm0
-; AVX512BW-NEXT: vmovdqu32 %zmm0, (%rax)
+; AVX512BW-NEXT: vmovdqu64 %zmm0, (%rax)
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%1 = load <32 x i16>, <32 x i16>* %a
@@ -1373,7 +1373,7 @@ define void @avg_v64i8_const(<64 x i8>*
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm0
; AVX512BW-NEXT: vpavgb {{.*}}(%rip), %zmm0, %zmm0
-; AVX512BW-NEXT: vmovdqu32 %zmm0, (%rax)
+; AVX512BW-NEXT: vmovdqu64 %zmm0, (%rax)
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%1 = load <64 x i8>, <64 x i8>* %a
@@ -1539,7 +1539,7 @@ define void @avg_v32i16_const(<32 x i16>
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm0
; AVX512BW-NEXT: vpavgw {{.*}}(%rip), %zmm0, %zmm0
-; AVX512BW-NEXT: vmovdqu32 %zmm0, (%rax)
+; AVX512BW-NEXT: vmovdqu64 %zmm0, (%rax)
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%1 = load <32 x i16>, <32 x i16>* %a
Modified: llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll?rev=322820&r1=322819&r2=322820&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll Wed Jan 17 23:44:09 2018
@@ -1838,7 +1838,7 @@ define i64 @test_insertelement_variable_
; SKX-NEXT: andl $63, %esi
; SKX-NEXT: testb %dil, %dil
; SKX-NEXT: vpmovm2b %k0, %zmm0
-; SKX-NEXT: vmovdqa32 %zmm0, (%rsp)
+; SKX-NEXT: vmovdqa64 %zmm0, (%rsp)
; SKX-NEXT: setne (%rsp,%rsi)
; SKX-NEXT: vpsllw $7, (%rsp), %zmm0
; SKX-NEXT: vpmovb2m %zmm0, %k0
@@ -2148,9 +2148,9 @@ define i96 @test_insertelement_variable_
; SKX-NEXT: andl $127, %eax
; SKX-NEXT: cmpb $0, 736(%rbp)
; SKX-NEXT: vpmovm2b %k1, %zmm0
-; SKX-NEXT: vmovdqa32 %zmm0, {{[0-9]+}}(%rsp)
+; SKX-NEXT: vmovdqa64 %zmm0, {{[0-9]+}}(%rsp)
; SKX-NEXT: vpmovm2b %k0, %zmm0
-; SKX-NEXT: vmovdqa32 %zmm0, (%rsp)
+; SKX-NEXT: vmovdqa64 %zmm0, (%rsp)
; SKX-NEXT: setne (%rsp,%rax)
; SKX-NEXT: vpsllw $7, {{[0-9]+}}(%rsp), %zmm0
; SKX-NEXT: vpmovb2m %zmm0, %k0
@@ -2265,9 +2265,9 @@ define i128 @test_insertelement_variable
; SKX-NEXT: andl $127, %esi
; SKX-NEXT: testb %dil, %dil
; SKX-NEXT: vpmovm2b %k1, %zmm0
-; SKX-NEXT: vmovdqa32 %zmm0, {{[0-9]+}}(%rsp)
+; SKX-NEXT: vmovdqa64 %zmm0, {{[0-9]+}}(%rsp)
; SKX-NEXT: vpmovm2b %k0, %zmm0
-; SKX-NEXT: vmovdqa32 %zmm0, (%rsp)
+; SKX-NEXT: vmovdqa64 %zmm0, (%rsp)
; SKX-NEXT: setne (%rsp,%rsi)
; SKX-NEXT: vpsllw $7, {{[0-9]+}}(%rsp), %zmm0
; SKX-NEXT: vpmovb2m %zmm0, %k0
Modified: llvm/trunk/test/CodeGen/X86/avx512-insert-extract_i1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-insert-extract_i1.ll?rev=322820&r1=322819&r2=322820&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-insert-extract_i1.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-insert-extract_i1.ll Wed Jan 17 23:44:09 2018
@@ -16,7 +16,7 @@ define zeroext i8 @test_extractelement_v
; SKX-NEXT: ## kill: def %edi killed %edi def %rdi
; SKX-NEXT: vpcmpnleub %zmm1, %zmm0, %k0
; SKX-NEXT: vpmovm2b %k0, %zmm0
-; SKX-NEXT: vmovdqa32 %zmm0, (%rsp)
+; SKX-NEXT: vmovdqa64 %zmm0, (%rsp)
; SKX-NEXT: andl $63, %edi
; SKX-NEXT: movzbl (%rsp,%rdi), %eax
; SKX-NEXT: andl $1, %eax
Modified: llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll?rev=322820&r1=322819&r2=322820&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll Wed Jan 17 23:44:09 2018
@@ -313,7 +313,7 @@ define void at test_int_x86_avx512_mask_sto
; CHECK: ## %bb.0:
; CHECK-NEXT: kmovw %edx, %k1
; CHECK-NEXT: vmovdqu32 %zmm0, (%rdi) {%k1}
-; CHECK-NEXT: vmovdqu32 %zmm0, (%rsi)
+; CHECK-NEXT: vmovdqu64 %zmm0, (%rsi)
; CHECK-NEXT: retq
call void @llvm.x86.avx512.mask.storeu.d.512(i8* %ptr1, <16 x i32> %x1, i16 %x2)
call void @llvm.x86.avx512.mask.storeu.d.512(i8* %ptr2, <16 x i32> %x1, i16 -1)
Modified: llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll?rev=322820&r1=322819&r2=322820&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll Wed Jan 17 23:44:09 2018
@@ -119,7 +119,7 @@ define void at test_int_x86_avx512_mask_sto
; AVX512BW: ## %bb.0:
; AVX512BW-NEXT: kmovq %rdx, %k1
; AVX512BW-NEXT: vmovdqu8 %zmm0, (%rdi) {%k1}
-; AVX512BW-NEXT: vmovdqu32 %zmm0, (%rsi)
+; AVX512BW-NEXT: vmovdqu64 %zmm0, (%rsi)
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
;
@@ -129,7 +129,7 @@ define void at test_int_x86_avx512_mask_sto
; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; AVX512F-32-NEXT: kmovq {{[0-9]+}}(%esp), %k1
; AVX512F-32-NEXT: vmovdqu8 %zmm0, (%ecx) {%k1}
-; AVX512F-32-NEXT: vmovdqu32 %zmm0, (%eax)
+; AVX512F-32-NEXT: vmovdqu64 %zmm0, (%eax)
; AVX512F-32-NEXT: vzeroupper
; AVX512F-32-NEXT: retl
call void @llvm.x86.avx512.mask.storeu.b.512(i8* %ptr1, <64 x i8> %x1, i64 %x2)
@@ -144,7 +144,7 @@ define void at test_int_x86_avx512_mask_sto
; AVX512BW: ## %bb.0:
; AVX512BW-NEXT: kmovd %edx, %k1
; AVX512BW-NEXT: vmovdqu16 %zmm0, (%rdi) {%k1}
-; AVX512BW-NEXT: vmovdqu32 %zmm0, (%rsi)
+; AVX512BW-NEXT: vmovdqu64 %zmm0, (%rsi)
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
;
@@ -154,7 +154,7 @@ define void at test_int_x86_avx512_mask_sto
; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
; AVX512F-32-NEXT: vmovdqu16 %zmm0, (%ecx) {%k1}
-; AVX512F-32-NEXT: vmovdqu32 %zmm0, (%eax)
+; AVX512F-32-NEXT: vmovdqu64 %zmm0, (%eax)
; AVX512F-32-NEXT: vzeroupper
; AVX512F-32-NEXT: retl
call void @llvm.x86.avx512.mask.storeu.w.512(i8* %ptr1, <32 x i16> %x1, i32 %x2)
Modified: llvm/trunk/test/CodeGen/X86/pr34605.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr34605.ll?rev=322820&r1=322819&r2=322820&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr34605.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr34605.ll Wed Jan 17 23:44:09 2018
@@ -19,7 +19,7 @@ define void @pr34605(i8* nocapture %s, i
; CHECK-NEXT: kandq %k1, %k0, %k1
; CHECK-NEXT: vmovdqu8 {{\.LCPI.*}}, %zmm0 {%k1} {z}
; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; CHECK-NEXT: vmovdqu32 %zmm0, (%eax)
+; CHECK-NEXT: vmovdqu64 %zmm0, (%eax)
; CHECK-NEXT: vmovups %zmm1, 64(%eax)
; CHECK-NEXT: vmovups %zmm1, 128(%eax)
; CHECK-NEXT: vmovups %zmm1, 192(%eax)
Modified: llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll?rev=322820&r1=322819&r2=322820&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll (original)
+++ llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll Wed Jan 17 23:44:09 2018
@@ -361,8 +361,8 @@ define void @interleaved_store_vf32_i8_s
; AVX512-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm4[2,3],ymm0[2,3]
; AVX512-NEXT: vinserti64x4 $1, %ymm5, %zmm2, %zmm2
; AVX512-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
-; AVX512-NEXT: vmovdqa32 %zmm0, 64(%rdi)
-; AVX512-NEXT: vmovdqa32 %zmm2, (%rdi)
+; AVX512-NEXT: vmovdqa64 %zmm0, 64(%rdi)
+; AVX512-NEXT: vmovdqa64 %zmm2, (%rdi)
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
%v1 = shufflevector <32 x i8> %x1, <32 x i8> %x2, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
@@ -420,7 +420,7 @@ define void @interleaved_store_vf16_i8_s
; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm3, %ymm1
; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm4, %ymm0
; AVX512-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
-; AVX512-NEXT: vmovdqa32 %zmm0, (%rdi)
+; AVX512-NEXT: vmovdqa64 %zmm0, (%rdi)
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
%v1 = shufflevector <16 x i8> %x1, <16 x i8> %x2, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
@@ -1390,7 +1390,7 @@ define void @interleaved_store_vf32_i8_s
; AVX512-NEXT: vpshufb %ymm4, %ymm0, %ymm0
; AVX512-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm1
; AVX512-NEXT: vmovdqu %ymm0, 64(%rdi)
-; AVX512-NEXT: vmovdqu32 %zmm1, (%rdi)
+; AVX512-NEXT: vmovdqu64 %zmm1, (%rdi)
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
%1 = shufflevector <32 x i8> %a, <32 x i8> %b, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
@@ -1538,9 +1538,9 @@ define void @interleaved_store_vf64_i8_s
; AVX512-NEXT: vinserti64x4 $1, %ymm5, %zmm3, %zmm1
; AVX512-NEXT: vinserti64x4 $1, %ymm7, %zmm6, %zmm3
; AVX512-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0
-; AVX512-NEXT: vmovdqu32 %zmm0, 128(%rdi)
-; AVX512-NEXT: vmovdqu32 %zmm3, 64(%rdi)
-; AVX512-NEXT: vmovdqu32 %zmm1, (%rdi)
+; AVX512-NEXT: vmovdqu64 %zmm0, 128(%rdi)
+; AVX512-NEXT: vmovdqu64 %zmm3, 64(%rdi)
+; AVX512-NEXT: vmovdqu64 %zmm1, (%rdi)
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
%1 = shufflevector <64 x i8> %a, <64 x i8> %b, <128 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, i32 79, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126, i32 127>
@@ -1874,10 +1874,10 @@ define void @interleaved_store_vf64_i8_s
; AVX512-NEXT: vinserti64x4 $1, %ymm7, %zmm6, %zmm3
; AVX512-NEXT: vinserti64x4 $1, %ymm9, %zmm8, %zmm4
; AVX512-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
-; AVX512-NEXT: vmovdqa32 %zmm0, 192(%rdi)
-; AVX512-NEXT: vmovdqa32 %zmm3, 64(%rdi)
-; AVX512-NEXT: vmovdqa32 %zmm4, 128(%rdi)
-; AVX512-NEXT: vmovdqa32 %zmm2, (%rdi)
+; AVX512-NEXT: vmovdqa64 %zmm0, 192(%rdi)
+; AVX512-NEXT: vmovdqa64 %zmm3, 64(%rdi)
+; AVX512-NEXT: vmovdqa64 %zmm4, 128(%rdi)
+; AVX512-NEXT: vmovdqa64 %zmm2, (%rdi)
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
%1 = shufflevector <64 x i8> %a, <64 x i8> %b, <128 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, i32 79, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126, i32 127>
Modified: llvm/trunk/test/Transforms/LoopVectorize/X86/avx512.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/X86/avx512.ll?rev=322820&r1=322819&r2=322820&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/LoopVectorize/X86/avx512.ll (original)
+++ llvm/trunk/test/Transforms/LoopVectorize/X86/avx512.ll Wed Jan 17 23:44:09 2018
@@ -7,7 +7,7 @@ target triple = "x86_64-apple-macosx10.9
; loop.
; CHECK-LABEL: f:
-; CHECK: vmovdqu32 %zmm{{.}},
+; CHECK: vmovdqu64 %zmm{{.}},
; CHECK-NOT: %ymm
define void @f(i32* %a, i32 %n) {
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