[PATCH] D42088: [x86] shrink 'and' immediate values by setting the high bits (PR35907)

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

Here's an example of the SimplifyDemandedBits failure that avoids the preliminary div transform in the existing test:

  define i32 @test3mul(i8 zeroext %x) {
    %z = zext i8 %x to i16
    %m = mul nuw nsw i16 %z, 171
    %s = lshr i16 %m, 9
    %z2 = zext i16 %s to i32
    %a = and i32 %z2, 127
    ret i32 %a
  }

So what happens is that we **do** remove the 'and' the first time we combine, and we have this after legalization:

         t4: i32 = AssertZext t2, ValueType:ch:i8
        t19: i16 = truncate t4
      t8: i16 = mul nuw nsw t19, Constant:i16<171>
    t11: i16 = srl t8, Constant:i8<9>
  t12: i32 = zero_extend t11

Now when we promote the 'srl' to 32-bit, we get:

  Promoting t11: i16 = srl t8, Constant:i8<9>
  Creating new node: t20: i32 = any_extend t8
  Creating constant: t21: i32 = Constant<65535>
  Creating new node: t22: i32 = and t20, Constant:i32<65535>
  Creating new node: t23: i32 = srl t22, Constant:i8<9>
  Creating new node: t24: i16 = truncate t23

When we combine the wider srl:

  Combining: t23: i32 = srl t26, Constant:i8<9>
  Creating constant: t27: i32 = Constant<127>
  Creating new node: t28: i32 = srl t20, Constant:i8<9>
  Creating new node: t29: i32 = and t28, Constant:i32<127>

Our 'and' is reincarnated! But notice that we used an 'any_extend' while promoting this to 32-bit. That means when we combine and check demanded bits on the 'and', we have:

       t8: i16 = mul nuw nsw t19, Constant:i16<171>
     t20: i32 = any_extend t8
   t28: i32 = srl t20, Constant:i8<9>
  t29: i32 = and t28, Constant: i32<127>

...so demanded bits can't kill the 'and'; the high bits are undef instead of zero. After the mul is promoted to 32-bits, we have:

        t4: i32 = AssertZext t2, ValueType:ch:i8
      t31: i32 = mul t4, Constant:i32<171>
    t28: i32 = srl t31, Constant:i8<9>
  t29: i32 = and t28, Constant:i32<127>

...but we don't revisit the later nodes for combining, so that's why we see the unnecessary when we get to Select(). Ideas about how to solve that?


https://reviews.llvm.org/D42088