[PATCH] D42128: [X86] Extend load-op-store fusion merge to ADC/SBB.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:2322
+      if ((Opc == X86ISD::ADD || Opc == X86ISD::SUB || Opc == X86ISD::ADC ||
+           Opc == X86ISD::SBB) &&
           ((MemVT != MVT::i8 && OperandV.getMinSignedBits() > 8 &&
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This part also needs a test case though I'm not even sure its mathematically sound.

For an 8-bit add for example, it turns (X + 128) into (X - (-128)) because since we can fit -128 into a sign extended 8-bit immediate, but not 128.

For an ADC, I think this code would try to turn (X + 128 + C) into (X - (-128) - C) since SBB subtracts the carry. So I don't think that works.


https://reviews.llvm.org/D42128