[PATCH] D38315: WIP: [ARM] Add f16 type support and code generation (part 1/2)

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer updated this revision to Diff 129957.
SjoerdMeijer added a reviewer: eli.friedman.
SjoerdMeijer added a subscriber: eli.friedman.
SjoerdMeijer added a comment.

This fixes most issues, now I am working on the only remaining failure 
fp16-promote.ll, which is missing an upconvert.

I've written an RFC to list here explaining the general approach:  
http://lists.llvm.org/pipermail/llvm-dev/2017-December/119467.html
And as I explained there, I want to add f16 as a legal type, and don't want any 
regressions for the storage-only type behaviour. That is the case, with one 
exception in fp16-promote.ll, where I accept one minor performance 
regression (not correctness) for now. That's a bitcast not being codegen'd,
which I still need to look into.

I've added @eli.friedman  as a reviewer here who commented on the RFC.
And as the patch is becoming big, and while I am fixing the last issue, I was wondering
if @eli.friedman and @olista01 can double-check the approach and look if we think this patch
is how we want to approach this. Of course, any other comments, nit picks are also
welcome too.

And just as another reminder, the motivation to do all this groundwork and plumbing, was to
enable instructions selection for Armv8.2-A FP16 instructions, i.e. let instruction selection work
on the f16 types. This patch, just a demonstrator (and a check), includes instruction selection for some
native f16 add and sub instructions.


https://reviews.llvm.org/D38315

Files:
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  lib/Target/ARM/ARMCallingConv.td
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMISelLowering.h
  lib/Target/ARM/ARMInstrVFP.td
  lib/Target/ARM/ARMRegisterInfo.td
  lib/Target/ARM/Disassembler/ARMDisassembler.cpp
  test/CodeGen/ARM/GlobalISel/arm-unsupported.ll
  test/CodeGen/ARM/fp16-args.ll
  test/CodeGen/ARM/fp16-instructions.ll
  test/CodeGen/ARM/fp16-v3.ll

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