[PATCH] D41863: [AArch64] Fix incorrect LD1 of 16-bit FP vectors in big endian

[Pablo Barrio via Phabricator via llvm-commits]

pbarrio updated this revision to Diff 129953.
pbarrio added a comment.

I have fixed the bug as olista01 suggested, which is more straightforward than
my previous fix.

There is still the question about why we require reversals in identity
conversions, but I believe that is affecting other conversions apart from the
v4i16->v4f16 ones. This is an optimization and can be handled in another patch,
as efriedma suggested.


Repository:
  rL LLVM

https://reviews.llvm.org/D41863

Files:
  lib/Target/AArch64/AArch64InstrInfo.td
  test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll


Index: test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll
===================================================================
--- test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll
+++ test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll
@@ -1099,3 +1099,17 @@
     store <16 x i8> %4, <16 x i8>* %q
     ret void
 }
+
+; CHECK-LABEL: test_v4f16_struct:
+%struct.struct1 = type { half, half, half, half }
+define %struct.struct1 @test_v4f16_struct(%struct.struct1* %ret) {
+entry:
+; CHECK: ld1 { {{v[0-9]+}}.2s }
+; CHECK: rev32
+; CHECK-NOT; rev64
+  %0 = bitcast %struct.struct1* %ret to <4 x half>*
+  %1 = load <4 x half>, <4 x half>* %0, align 2
+  %2 = extractelement <4 x half> %1, i32 0
+  %.fca.0.insert = insertvalue %struct.struct1 undef, half %2, 0
+  ret %struct.struct1 %.fca.0.insert
+}
Index: lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- lib/Target/AArch64/AArch64InstrInfo.td
+++ lib/Target/AArch64/AArch64InstrInfo.td
@@ -5847,7 +5847,7 @@
 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))),
                              (v4f16 (REV64v4i16 FPR64:$src))>;
 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))),
-                             (v4f16 (REV64v4i16 FPR64:$src))>;
+                             (v4f16 (REV32v4i16 FPR64:$src))>;
 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))),
                              (v4f16 (REV64v4i16 FPR64:$src))>;
 def : Pat<(v4f16 (bitconvert (v8i8  FPR64:$src))),


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