[llvm] r322457 - [x86] auto-generate complete checks; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 14 09:47:40 PST 2018
Author: spatel
Date: Sun Jan 14 09:47:40 2018
New Revision: 322457
URL: http://llvm.org/viewvc/llvm-project?rev=322457&view=rev
Log:
[x86] auto-generate complete checks; NFC
Modified:
llvm/trunk/test/CodeGen/X86/x86-64-baseptr.ll
llvm/trunk/test/CodeGen/X86/zext-fold.ll
Modified: llvm/trunk/test/CodeGen/X86/x86-64-baseptr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-64-baseptr.ll?rev=322457&r1=322456&r2=322457&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/x86-64-baseptr.ll (original)
+++ llvm/trunk/test/CodeGen/X86/x86-64-baseptr.ll Sun Jan 14 09:47:40 2018
@@ -1,21 +1,61 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-pc-linux -stackrealign -stack-alignment=32 < %s | FileCheck %s
; RUN: llc -mtriple=x86_64-pc-linux-gnux32 -stackrealign -stack-alignment=32 < %s | FileCheck -check-prefix=X32ABI %s
+
; This should run with NaCl as well ( -mtriple=x86_64-pc-nacl ) but currently doesn't due to PR22655
; Make sure the correct register gets set up as the base pointer
; This should be rbx for x64 and 64-bit NaCl and ebx for x32
-; CHECK-LABEL: base
-; CHECK: subq $32, %rsp
-; CHECK: movq %rsp, %rbx
-; X32ABI-LABEL: base
-; X32ABI: subl $32, %esp
-; X32ABI: movl %esp, %ebx
; NACL-LABEL: base
; NACL: subq $32, %rsp
; NACL: movq %rsp, %rbx
declare i32 @helper() nounwind
define void @base() #0 {
+; CHECK-LABEL: base:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: movq %rsp, %rbp
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: andq $-32, %rsp
+; CHECK-NEXT: subq $32, %rsp
+; CHECK-NEXT: movq %rsp, %rbx
+; CHECK-NEXT: callq helper
+; CHECK-NEXT: movl %eax, %eax
+; CHECK-NEXT: leaq 31(,%rax,4), %rax
+; CHECK-NEXT: movabsq $34359738336, %rcx # imm = 0x7FFFFFFE0
+; CHECK-NEXT: andq %rax, %rcx
+; CHECK-NEXT: movq %rsp, %rax
+; CHECK-NEXT: movq %rax, %rdx
+; CHECK-NEXT: subq %rcx, %rdx
+; CHECK-NEXT: negq %rcx
+; CHECK-NEXT: movq %rdx, %rsp
+; CHECK-NEXT: movl $0, (%rax,%rcx)
+; CHECK-NEXT: leaq -8(%rbp), %rsp
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+;
+; X32ABI-LABEL: base:
+; X32ABI: # %bb.0: # %entry
+; X32ABI-NEXT: pushq %rbp
+; X32ABI-NEXT: movl %esp, %ebp
+; X32ABI-NEXT: andl $-32, %esp
+; X32ABI-NEXT: subl $32, %esp
+; X32ABI-NEXT: movl %esp, %ebx
+; X32ABI-NEXT: callq helper
+; X32ABI-NEXT: # kill: def %eax killed %eax def %rax
+; X32ABI-NEXT: movl %esp, %ecx
+; X32ABI-NEXT: leal 31(,%rax,4), %eax
+; X32ABI-NEXT: andl $-32, %eax
+; X32ABI-NEXT: movl %ecx, %edx
+; X32ABI-NEXT: subl %eax, %edx
+; X32ABI-NEXT: movl %edx, %esp
+; X32ABI-NEXT: negl %eax
+; X32ABI-NEXT: movl $0, (%ecx,%eax)
+; X32ABI-NEXT: movl %ebp, %esp
+; X32ABI-NEXT: popq %rbp
+; X32ABI-NEXT: retq
entry:
%k = call i32 @helper()
%a = alloca i32, i32 %k, align 4
@@ -23,4 +63,4 @@ entry:
ret void
}
-attributes #0 = { nounwind uwtable "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"}
+attributes #0 = { nounwind "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"}
Modified: llvm/trunk/test/CodeGen/X86/zext-fold.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/zext-fold.ll?rev=322457&r1=322456&r2=322457&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/zext-fold.ll (original)
+++ llvm/trunk/test/CodeGen/X86/zext-fold.ll Sun Jan 14 09:47:40 2018
@@ -1,17 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-linux -enable-misched=false | FileCheck %s
;; Simple case
define i32 @test1(i8 %x) nounwind readnone {
+; CHECK-LABEL: test1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: andl $224, %eax
+; CHECK-NEXT: retl
%A = and i8 %x, -32
%B = zext i8 %A to i32
ret i32 %B
}
-; CHECK: test1
-; CHECK: movzbl
-; CHECK-NEXT: andl {{.*}}224
;; Multiple uses of %x but easily extensible.
define i32 @test2(i8 %x) nounwind readnone {
+; CHECK-LABEL: test2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movl %eax, %ecx
+; CHECK-NEXT: andl $224, %ecx
+; CHECK-NEXT: orl $63, %eax
+; CHECK-NEXT: addl %ecx, %eax
+; CHECK-NEXT: retl
%A = and i8 %x, -32
%B = zext i8 %A to i32
%C = or i8 %x, 63
@@ -19,24 +30,25 @@ define i32 @test2(i8 %x) nounwind readno
%E = add i32 %B, %D
ret i32 %E
}
-; CHECK: test2
-; CHECK: movzbl
-; CHECK: andl $224
-; CHECK: orl $63
declare void @use(i32, i8)
;; Multiple uses of %x where we shouldn't extend the load.
define void @test3(i8 %x) nounwind readnone {
+; CHECK-LABEL: test3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: subl $12, %esp
+; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: subl $8, %esp
+; CHECK-NEXT: pushl %eax
+; CHECK-NEXT: andl $224, %eax
+; CHECK-NEXT: pushl %eax
+; CHECK-NEXT: calll use
+; CHECK-NEXT: addl $28, %esp
+; CHECK-NEXT: retl
%A = and i8 %x, -32
%B = zext i8 %A to i32
call void @use(i32 %B, i8 %x)
ret void
}
-; CHECK: test3
-; CHECK: movzbl {{[0-9]+}}(%esp), [[REGISTER:%e[a-z]{2}]]
-; CHECK: subl $8, %esp
-; CHECK-NEXT: pushl [[REGISTER]]
-; CHECK-NEXT: andl $224, [[REGISTER]]
-; CHECK-NEXT: pushl [[REGISTER]]
-; CHECK-NEXT: call{{.*}}use
+
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