[llvm] r322392 - [AArch64] Fix scheduling resources for post indexed loads and stores

[Evandro Menezes via llvm-commits]

Author: evandro
Date: Fri Jan 12 11:20:11 2018
New Revision: 322392

URL: http://llvm.org/viewvc/llvm-project?rev=322392&view=rev
Log:
[AArch64] Fix scheduling resources for post indexed loads and stores

Fix typos in the default scheduling resources when using the post indexed
addressing modes.

Differential revision: https://reviews.llvm.org/D40511

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td

Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=322392&r1=322391&r2=322392&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td Fri Jan 12 11:20:11 2018
@@ -3376,7 +3376,7 @@ class LoadPostIdx<bits<2> sz, bit V, bit
                       (outs GPR64sp:$wback, regtype:$Rt),
                       (ins GPR64sp:$Rn, simm9:$offset),
                       asm, "$Rn = $wback, at earlyclobber $wback", []>,
-      Sched<[WriteLD, WriteI]>;
+      Sched<[WriteLD, WriteAdr]>;
 
 let mayStore = 1, mayLoad = 0 in
 class StorePostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
@@ -3387,7 +3387,7 @@ class StorePostIdx<bits<2> sz, bit V, bi
                        asm, "$Rn = $wback, at earlyclobber $wback",
       [(set GPR64sp:$wback,
             (storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,
-    Sched<[WriteAdr, WriteST, ReadAdrBase]>;
+    Sched<[WriteAdr, WriteST]>;
 } // hasSideEffects = 0