[llvm] r322169 - [ARM GlobalISel] Map G_FNEG to the FPR bank

[Diana Picus via llvm-commits]

Author: rovka
Date: Wed Jan 10 03:13:31 2018
New Revision: 322169

URL: http://llvm.org/viewvc/llvm-project?rev=322169&view=rev
Log:
[ARM GlobalISel] Map G_FNEG to the FPR bank

Modified:
    llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
    llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=322169&r1=322168&r2=322169&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Wed Jan 10 03:13:31 2018
@@ -263,7 +263,8 @@ ARMRegisterBankInfo::getInstrMapping(con
   case G_FADD:
   case G_FSUB:
   case G_FMUL:
-  case G_FDIV: {
+  case G_FDIV:
+  case G_FNEG: {
     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
     OperandsMapping =Ty.getSizeInBits() == 64
                           ? &ARM::ValueMappings[ARM::DPR3OpsIdx]

Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir?rev=322169&r1=322168&r2=322169&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir Wed Jan 10 03:13:31 2018
@@ -59,6 +59,9 @@
   define void @test_fdiv_s32() #0 { ret void }
   define void @test_fdiv_s64() #0 { ret void }
 
+  define void @test_fneg_s32() #0 { ret void }
+  define void @test_fneg_s64() #0 { ret void }
+
   define void @test_soft_fp_s64() #0 { ret void }
 
   attributes #0 = { "target-features"="+vfp2"}
@@ -1092,6 +1095,52 @@ body:             |
     BX_RET 14, %noreg, implicit %d0
 
 ...
+---
+name:            test_fneg_s32
+# CHECK-LABEL: name: test_fneg_s32
+legalized:       true
+regBankSelected: false
+selected:        false
+# CHECK: registers:
+# CHECK: - { id: 0, class: fprb, preferred-register: '' }
+# CHECK: - { id: 1, class: fprb, preferred-register: '' }
+
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0:
+    liveins: %s0
+
+    %0(s32) = COPY %s0
+    %1(s32) = G_FNEG %0
+    %s0 = COPY %1(s32)
+    BX_RET 14, %noreg, implicit %s0
+
+...
+---
+name:            test_fneg_s64
+# CHECK-LABEL: name: test_fneg_s64
+legalized:       true
+regBankSelected: false
+selected:        false
+# CHECK: registers:
+# CHECK: - { id: 0, class: fprb, preferred-register: '' }
+# CHECK: - { id: 1, class: fprb, preferred-register: '' }
+
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0:
+    liveins: %d0
+
+    %0(s64) = COPY %d0
+    %1(s64) = G_FNEG %0
+    %d0 = COPY %1(s64)
+    BX_RET 14, %noreg, implicit %d0
+
+...
 ---
 name:            test_soft_fp_s64
 # CHECK-LABEL: name: test_soft_fp_s64