[PATCH] D41443: [AArch64][SVE] Asm: Add predicated ADD/SUB instructions

[Florian Hahn via Phabricator via llvm-commits]

fhahn added inline comments.


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Comment at: lib/Target/AArch64/AArch64SVEInstrInfo.td:18
 
+  defm ADD_ZPmZ  : sve_int_bin_pred_arit_0<0b000, "add">;
+  defm SUB_ZPmZ  : sve_int_bin_pred_arit_0<0b001, "sub">;
----------------
It takes 4 registers, shouldn't the name be `ADD_ZPmZZ`? Same below


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Comment at: lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp:94
                                            const void *Decode);
-LLVM_ATTRIBUTE_UNUSED static DecodeStatus
-DecodePPR_3bRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address,
-                          const void *Decode);
+static DecodeStatus DecodePPR_3bRegisterClass(llvm::MCInst &Inst,
+                                              unsigned RegNo, uint64_t Address,
----------------
No need for `llvm::` here.


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Comment at: test/MC/AArch64/SVE/add-diagnostics.s:21
+
+// error: restricted predicate has range [0, 7].
+add z22.b, p8/m, z22.b, z11.b
----------------
IIRC you changed the comment/grouping structure in a previous patch. Could you use the same here?

// Comment about case
add 8bit,
add a16bit,
...
...



https://reviews.llvm.org/D41443