[PATCH] D41772: [AArch64] optimise v4f16 FCMPs to utilise vector instructions

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer accepted this revision.
SjoerdMeijer added a comment.
This revision is now accepted and ready to land.

Thanks, looks good to me. Just a few nits inlined, no need for another review.



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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:7296
+
+  // Make v4f16 (only) fcmp operations utilise vector instructions
+  if (LHS.getValueType().getVectorElementType() == MVT::f16) {
----------------
Nit: perhaps a "TODO remark" here that v8f16 could be optimised as well but is a bit more complicated? 


================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:7303
+      DAG.ReplaceAllUsesWith(Op, NewSetcc);
+
+      CmpVT = MVT::v4i32;
----------------
Nit: newline not necessary?


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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:7305
+      CmpVT = MVT::v4i32;
+    } else {
+      return SDValue();
----------------
Coding style nit: you don't need the brackets for the else-clause (you can check the coding style with clang-format)


https://reviews.llvm.org/D41772