[llvm] r321897 - [Hexagon] Even simpler patterns for sign- and zero-extending HVX vectors

Krzysztof Parzyszek via llvm-commits llvm-commits at lists.llvm.org
Fri Jan 5 12:49:26 PST 2018


Author: kparzysz
Date: Fri Jan  5 12:49:26 2018
New Revision: 321897

URL: http://llvm.org/viewvc/llvm-project?rev=321897&view=rev
Log:
[Hexagon] Even simpler patterns for sign- and zero-extending HVX vectors

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td

Modified: llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td?rev=321897&r1=321896&r2=321897&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td Fri Jan  5 12:49:26 2018
@@ -2924,22 +2924,10 @@ let Predicates = [UseHVX] in {
 def HexagonVZERO: SDNode<"HexagonISD::VZERO", SDTVecLeaf>;
 def vzero: PatFrag<(ops), (HexagonVZERO)>;
 
-def VSxtb: OutPatFrag<(ops node:$Vs),
-           (V6_vshuffvdd (HiVec (V6_vsb $Vs)),
-                         (LoVec (V6_vsb $Vs)),
-                         (A2_tfrsi -2))>;
-def VSxth: OutPatFrag<(ops node:$Vs),
-           (V6_vshuffvdd (HiVec (V6_vsh $Vs)),
-                         (LoVec (V6_vsh $Vs)),
-                         (A2_tfrsi -4))>;
-def VZxtb: OutPatFrag<(ops node:$Vs),
-           (V6_vshuffvdd (HiVec (V6_vzb $Vs)),
-                         (LoVec (V6_vzb $Vs)),
-                         (A2_tfrsi -2))>;
-def VZxth: OutPatFrag<(ops node:$Vs),
-           (V6_vshuffvdd (HiVec (V6_vzh $Vs)),
-                         (LoVec (V6_vzh $Vs)),
-                         (A2_tfrsi -4))>;
+def VSxtb: OutPatFrag<(ops node:$Vs), (V6_vunpackb  $Vs)>;
+def VSxth: OutPatFrag<(ops node:$Vs), (V6_vunpackh  $Vs)>;
+def VZxtb: OutPatFrag<(ops node:$Vs), (V6_vunpackub $Vs)>;
+def VZxth: OutPatFrag<(ops node:$Vs), (V6_vunpackuh $Vs)>;
 
 let Predicates = [UseHVX] in {
   def: Pat<(VecI8  vzero), (V6_vd0)>;




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