[llvm] r321823 - [X86] Add scalar undef sdiv/srem/udiv/urem combine tests
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 4 13:33:19 PST 2018
Author: rksimon
Date: Thu Jan 4 13:33:19 2018
New Revision: 321823
URL: http://llvm.org/viewvc/llvm-project?rev=321823&view=rev
Log:
[X86] Add scalar undef sdiv/srem/udiv/urem combine tests
Modified:
llvm/trunk/test/CodeGen/X86/combine-sdiv.ll
llvm/trunk/test/CodeGen/X86/combine-srem.ll
llvm/trunk/test/CodeGen/X86/combine-udiv.ll
llvm/trunk/test/CodeGen/X86/combine-urem.ll
Modified: llvm/trunk/test/CodeGen/X86/combine-sdiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-sdiv.ll?rev=321823&r1=321822&r2=321823&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-sdiv.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-sdiv.ll Thu Jan 4 13:33:19 2018
@@ -4,6 +4,15 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX2
; fold (sdiv undef, x) -> 0
+define i32 @combine_sdiv_undef0(i32 %x) {
+; CHECK-LABEL: combine_sdiv_undef0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: retq
+ %1 = sdiv i32 undef, %x
+ ret i32 %1
+}
+
define <4 x i32> @combine_vec_sdiv_undef0(<4 x i32> %x) {
; CHECK-LABEL: combine_vec_sdiv_undef0:
; CHECK: # %bb.0:
@@ -13,6 +22,14 @@ define <4 x i32> @combine_vec_sdiv_undef
}
; fold (sdiv x, undef) -> undef
+define i32 @combine_sdiv_undef1(i32 %x) {
+; CHECK-LABEL: combine_sdiv_undef1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: retq
+ %1 = sdiv i32 %x, undef
+ ret i32 %1
+}
+
define <4 x i32> @combine_vec_sdiv_undef1(<4 x i32> %x) {
; CHECK-LABEL: combine_vec_sdiv_undef1:
; CHECK: # %bb.0:
@@ -22,6 +39,15 @@ define <4 x i32> @combine_vec_sdiv_undef
}
; fold (sdiv x, 1) -> x
+define i32 @combine_sdiv_by_one(i32 %x) {
+; CHECK-LABEL: combine_sdiv_by_one:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: retq
+ %1 = sdiv i32 %x, 1
+ ret i32 %1
+}
+
define <4 x i32> @combine_vec_sdiv_by_one(<4 x i32> %x) {
; CHECK-LABEL: combine_vec_sdiv_by_one:
; CHECK: # %bb.0:
@@ -31,6 +57,16 @@ define <4 x i32> @combine_vec_sdiv_by_on
}
; fold (sdiv x, -1) -> 0 - x
+define i32 @combine_sdiv_by_negone(i32 %x) {
+; CHECK-LABEL: combine_sdiv_by_negone:
+; CHECK: # %bb.0:
+; CHECK-NEXT: negl %edi
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: retq
+ %1 = sdiv i32 %x, -1
+ ret i32 %1
+}
+
define <4 x i32> @combine_vec_sdiv_by_negone(<4 x i32> %x) {
; SSE-LABEL: combine_vec_sdiv_by_negone:
; SSE: # %bb.0:
Modified: llvm/trunk/test/CodeGen/X86/combine-srem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-srem.ll?rev=321823&r1=321822&r2=321823&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-srem.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-srem.ll Thu Jan 4 13:33:19 2018
@@ -4,6 +4,15 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX2
; fold (srem undef, x) -> 0
+define i32 @combine_srem_undef0(i32 %x) {
+; CHECK-LABEL: combine_srem_undef0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: retq
+ %1 = srem i32 undef, %x
+ ret i32 %1
+}
+
define <4 x i32> @combine_vec_srem_undef0(<4 x i32> %x) {
; CHECK-LABEL: combine_vec_srem_undef0:
; CHECK: # %bb.0:
@@ -13,6 +22,14 @@ define <4 x i32> @combine_vec_srem_undef
}
; fold (srem x, undef) -> undef
+define i32 @combine_srem_undef1(i32 %x) {
+; CHECK-LABEL: combine_srem_undef1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: retq
+ %1 = srem i32 %x, undef
+ ret i32 %1
+}
+
define <4 x i32> @combine_vec_srem_undef1(<4 x i32> %x) {
; CHECK-LABEL: combine_vec_srem_undef1:
; CHECK: # %bb.0:
Modified: llvm/trunk/test/CodeGen/X86/combine-udiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-udiv.ll?rev=321823&r1=321822&r2=321823&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-udiv.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-udiv.ll Thu Jan 4 13:33:19 2018
@@ -4,6 +4,15 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX2
; fold (udiv undef, x) -> 0
+define i32 @combine_udiv_undef0(i32 %x) {
+; CHECK-LABEL: combine_udiv_undef0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: retq
+ %1 = udiv i32 undef, %x
+ ret i32 %1
+}
+
define <4 x i32> @combine_vec_udiv_undef0(<4 x i32> %x) {
; CHECK-LABEL: combine_vec_udiv_undef0:
; CHECK: # %bb.0:
@@ -13,6 +22,14 @@ define <4 x i32> @combine_vec_udiv_undef
}
; fold (udiv x, undef) -> undef
+define i32 @combine_udiv_undef1(i32 %x) {
+; CHECK-LABEL: combine_udiv_undef1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: retq
+ %1 = udiv i32 %x, undef
+ ret i32 %1
+}
+
define <4 x i32> @combine_vec_udiv_undef1(<4 x i32> %x) {
; CHECK-LABEL: combine_vec_udiv_undef1:
; CHECK: # %bb.0:
Modified: llvm/trunk/test/CodeGen/X86/combine-urem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-urem.ll?rev=321823&r1=321822&r2=321823&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-urem.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-urem.ll Thu Jan 4 13:33:19 2018
@@ -4,6 +4,15 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX2
; fold (urem undef, x) -> 0
+define i32 @combine_urem_undef0(i32 %x) {
+; CHECK-LABEL: combine_urem_undef0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: retq
+ %1 = urem i32 undef, %x
+ ret i32 %1
+}
+
define <4 x i32> @combine_vec_urem_undef0(<4 x i32> %x) {
; CHECK-LABEL: combine_vec_urem_undef0:
; CHECK: # %bb.0:
@@ -13,6 +22,14 @@ define <4 x i32> @combine_vec_urem_undef
}
; fold (urem x, undef) -> undef
+define i32 @combine_urem_undef1(i32 %x) {
+; CHECK-LABEL: combine_urem_undef1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: retq
+ %1 = urem i32 %x, undef
+ ret i32 %1
+}
+
define <4 x i32> @combine_vec_urem_undef1(<4 x i32> %x) {
; CHECK-LABEL: combine_vec_urem_undef1:
; CHECK: # %bb.0:
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