[PATCH] D40805: [RISCV] Support for varargs

[Leslie Zhai via Phabricator via llvm-commits]

xiangzhai added inline comments.


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Comment at: lib/Target/RISCV/RISCVISelLowering.cpp:446
+    unsigned RegIdx = State.getFirstUnallocated(ArgGPRs);
+    if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1) {
+      State.AllocateReg(ArgGPRs);
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`RegIdx % 2 == 1` is an odd register, not an even, but the comment is "ensure it is assigned to an even register".


https://reviews.llvm.org/D40805