[PATCH] D41447: [AArch64][SVE] Asm: Negative tests for predicated ADD/SUB register constraints

[Florian Hahn via Phabricator via llvm-commits]

fhahn added inline comments.


================
Comment at: test/MC/AArch64/SVE/sub-diagnostics.s:57
+
+// Source and Destination Registers must match
+sub z25.b, p4/m, z26.b, z2.b
----------------
nit: I think it would be slightly clearer if the grouping was like this: 


```
// Source and Destination Registers must match

sub z25.b, p4/m, z26.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: sub z25.b, p4/m, z26.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

.....

sub z2.d, p5/m, z3.d, z11.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: sub z2.d, p5/m, z3.d, z11.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------
```




https://reviews.llvm.org/D41447