[llvm] r321607 - [X86][SSE] Don't vectorize splat buildvector of binops (PR30780)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 31 09:07:48 PST 2017
Author: rksimon
Date: Sun Dec 31 09:07:47 2017
New Revision: 321607
URL: http://llvm.org/viewvc/llvm-project?rev=321607&view=rev
Log:
[X86][SSE] Don't vectorize splat buildvector of binops (PR30780)
Don't combine buildvector(binop(),binop(),binop(),binop()) -> binop(buildvector(), buildvector()) if its a splat - keep the binop scalar and just splat the result to avoid large vector constants.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/test/CodeGen/X86/build-vector-128.ll
llvm/trunk/test/CodeGen/X86/build-vector-256.ll
llvm/trunk/test/CodeGen/X86/vector-pcmp.ll
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=321607&r1=321606&r2=321607&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Dec 31 09:07:47 2017
@@ -7723,6 +7723,10 @@ static SDValue lowerBuildVectorToBitOp(B
case ISD::AND:
case ISD::XOR:
case ISD::OR:
+ // Don't do this if the buildvector is a splat - we'd replace one
+ // constant with an entire vector.
+ if (Op->getSplatValue())
+ return SDValue();
if (!TLI.isOperationLegalOrPromote(Opcode, VT))
return SDValue();
break;
Modified: llvm/trunk/test/CodeGen/X86/build-vector-128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/build-vector-128.ll?rev=321607&r1=321606&r2=321607&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/build-vector-128.ll (original)
+++ llvm/trunk/test/CodeGen/X86/build-vector-128.ll Sun Dec 31 09:07:47 2017
@@ -468,18 +468,12 @@ define <4 x i32> @test_buildvector_v4i32
; SSE-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; SSE-32-NEXT: retl
;
-; SSE2-64-LABEL: test_buildvector_v4i32_splat_zext_i8:
-; SSE2-64: # %bb.0:
-; SSE2-64-NEXT: movd %edi, %xmm0
-; SSE2-64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; SSE2-64-NEXT: pand {{.*}}(%rip), %xmm0
-; SSE2-64-NEXT: retq
-;
-; SSE41-64-LABEL: test_buildvector_v4i32_splat_zext_i8:
-; SSE41-64: # %bb.0:
-; SSE41-64-NEXT: movd %edi, %xmm0
-; SSE41-64-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero
-; SSE41-64-NEXT: retq
+; SSE-64-LABEL: test_buildvector_v4i32_splat_zext_i8:
+; SSE-64: # %bb.0:
+; SSE-64-NEXT: movzbl %dil, %eax
+; SSE-64-NEXT: movd %eax, %xmm0
+; SSE-64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
+; SSE-64-NEXT: retq
;
; AVX1-32-LABEL: test_buildvector_v4i32_splat_zext_i8:
; AVX1-32: # %bb.0:
@@ -490,8 +484,9 @@ define <4 x i32> @test_buildvector_v4i32
;
; AVX1-64-LABEL: test_buildvector_v4i32_splat_zext_i8:
; AVX1-64: # %bb.0:
-; AVX1-64-NEXT: vmovd %edi, %xmm0
-; AVX1-64-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero
+; AVX1-64-NEXT: movzbl %dil, %eax
+; AVX1-64-NEXT: vmovd %eax, %xmm0
+; AVX1-64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX1-64-NEXT: retq
;
; AVX2-32-LABEL: test_buildvector_v4i32_splat_zext_i8:
Modified: llvm/trunk/test/CodeGen/X86/build-vector-256.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/build-vector-256.ll?rev=321607&r1=321606&r2=321607&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/build-vector-256.ll (original)
+++ llvm/trunk/test/CodeGen/X86/build-vector-256.ll Sun Dec 31 09:07:47 2017
@@ -461,10 +461,10 @@ define <8 x i32> @test_buildvector_v8i32
;
; AVX1-64-LABEL: test_buildvector_v8i32_splat_zext_i8:
; AVX1-64: # %bb.0:
-; AVX1-64-NEXT: vmovd %edi, %xmm0
+; AVX1-64-NEXT: movzbl %dil, %eax
+; AVX1-64-NEXT: vmovd %eax, %xmm0
; AVX1-64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX1-64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; AVX1-64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; AVX1-64-NEXT: retq
;
; AVX2-32-LABEL: test_buildvector_v8i32_splat_zext_i8:
Modified: llvm/trunk/test/CodeGen/X86/vector-pcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-pcmp.ll?rev=321607&r1=321606&r2=321607&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector-pcmp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vector-pcmp.ll Sun Dec 31 09:07:47 2017
@@ -84,47 +84,28 @@ define <2 x i64> @test_pcmpgtq(<2 x i64>
}
define <1 x i128> @test_strange_type(<1 x i128> %x) {
-; SSE2-LABEL: test_strange_type:
-; SSE2: # %bb.0:
-; SSE2-NEXT: sarq $63, %rsi
-; SSE2-NEXT: movq %rsi, %xmm0
-; SSE2-NEXT: notq %rsi
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
-; SSE2-NEXT: pcmpeqd %xmm1, %xmm1
-; SSE2-NEXT: pxor %xmm0, %xmm1
-; SSE2-NEXT: movq %xmm1, %rax
-; SSE2-NEXT: movq %rsi, %rdx
-; SSE2-NEXT: retq
-;
-; SSE42-LABEL: test_strange_type:
-; SSE42: # %bb.0:
-; SSE42-NEXT: sarq $63, %rsi
-; SSE42-NEXT: movq %rsi, %xmm0
-; SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
-; SSE42-NEXT: pcmpeqd %xmm1, %xmm1
-; SSE42-NEXT: pxor %xmm0, %xmm1
-; SSE42-NEXT: movq %xmm1, %rax
-; SSE42-NEXT: pextrq $1, %xmm1, %rdx
-; SSE42-NEXT: retq
+; SSE-LABEL: test_strange_type:
+; SSE: # %bb.0:
+; SSE-NEXT: sarq $63, %rsi
+; SSE-NEXT: notq %rsi
+; SSE-NEXT: movq %rsi, %rax
+; SSE-NEXT: movq %rsi, %rdx
+; SSE-NEXT: retq
;
; AVX1-LABEL: test_strange_type:
; AVX1: # %bb.0:
; AVX1-NEXT: sarq $63, %rsi
-; AVX1-NEXT: vmovq %rsi, %xmm0
-; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
-; AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
-; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vmovq %xmm0, %rax
-; AVX1-NEXT: vpextrq $1, %xmm0, %rdx
+; AVX1-NEXT: notq %rsi
+; AVX1-NEXT: movq %rsi, %rax
+; AVX1-NEXT: movq %rsi, %rdx
; AVX1-NEXT: retq
;
; AVX2-LABEL: test_strange_type:
; AVX2: # %bb.0:
; AVX2-NEXT: sarq $63, %rsi
+; AVX2-NEXT: notq %rsi
; AVX2-NEXT: vmovq %rsi, %xmm0
; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
-; AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
-; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: vpextrq $1, %xmm0, %rdx
; AVX2-NEXT: retq
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