[PATCH] D41643: [DAG] Fix for Bug PR34620 - Allow SimplifyDemandedBits to look through bitcasted constants

Sam Conrad via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sat Dec 30 19:35:56 PST 2017


sameconrad created this revision.
sameconrad added a reviewer: RKSimon.

Allow SimplifyDemandedBits to use TargetLoweringOpt::computeKnownBits to look through bitcasted constants.  This can help simplifying in some cases where bitcasts of constants generated during or after legalization can't be folded away, and thus didn't get picked up by SimplifyDemandedBits.   This fixes PR34620, where a redundant pand created during legalization from lowering and lshr <16xi8> wasn't being simplified due to the presence of a bitcasted build_vector as an operand.


https://reviews.llvm.org/D41643

Files:
  lib/CodeGen/SelectionDAG/TargetLowering.cpp
  test/CodeGen/X86/combine-and.ll


Index: test/CodeGen/X86/combine-and.ll
===================================================================
--- test/CodeGen/X86/combine-and.ll
+++ test/CodeGen/X86/combine-and.ll
@@ -281,7 +281,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    psrlw $1, %xmm0
 ; CHECK-NEXT:    pand {{.*}}(%rip), %xmm0
-; CHECK-NEXT:    pand {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    paddb %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %1 = lshr <16 x i8> %a0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
Index: lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1220,6 +1220,12 @@
                                                  Sign, ShAmt));
       }
     }
+    // If this is a bitcast of a constant, let computeKnownBits handle it.  Only
+    // do this on a recursive call where Known may be useful to the caller.
+    if (Depth > 0 && isConstOrConstSplat(Op.getOperand(0))) {
+      TLO.DAG.computeKnownBits(Op, Known, Depth);
+      return false;
+    }
     break;
   case ISD::ADD:
   case ISD::MUL:


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