[llvm] r321268 - [X86] Add (and (or x, C), D) -> D iff (C & D) == D non-splat vector test

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Thu Dec 21 06:33:40 2017
New Revision: 321268

URL: http://llvm.org/viewvc/llvm-project?rev=321268&view=rev
Log:
[X86] Add (and (or x, C), D) -> D iff (C & D) == D non-splat vector test

Modified:
    llvm/trunk/test/CodeGen/X86/combine-and.ll

Modified: llvm/trunk/test/CodeGen/X86/combine-and.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-and.ll?rev=321268&r1=321267&r2=321268&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-and.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-and.ll Thu Dec 21 06:33:40 2017
@@ -220,6 +220,17 @@ define <4 x i32> @and_or_v4i32(<4 x i32>
   ret <4 x i32> %2
 }
 
+define <8 x i16> @and_or_v8i16(<8 x i16> %a0) {
+; CHECK-LABEL: and_or_v8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    orps {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    retq
+  %1 = or <8 x i16> %a0, <i16 255, i16 127, i16 63, i16 31, i16 15, i16 31, i16 63, i16 -1>
+  %2 = and <8 x i16> %1, <i16 15, i16 7, i16 3, i16 1, i16 14, i16 10, i16 2, i16 32767>
+  ret <8 x i16> %2
+}
+
 ;
 ; known bits folding
 ;