[PATCH] D41441: [AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors.
Florian Hahn via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 21 04:02:08 PST 2017
fhahn added reviewers: olista01, SjoerdMeijer, javed.absar.
fhahn added a comment.
Looks reasonable to me. Adding a couple of more people who might have additional suggestions.
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