[PATCH] D41467: PR35710: Nary reassociation falls into infinite loop
Evgeny Stupachenko via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 20 14:50:02 PST 2017
evstupac created this revision.
evstupac added reviewers: jingyue, marcello.maggioni.
The following example:
define i8 @foo(i8 %v) local_unnamed_addr #0 {
region.0:
%0 = mul nsw i8 16, %v
%1 = mul nsw i8 0, %0
%2 = mul nsw i8 1, %1
ret i8 %2
}
Causes nary reassociation to fall into infinite loop.
The root cause is in overflowed SCEV expression (16*v)*(16*v) - which is 0 for "i8" type.
The patch inserts a check to avoid the case.
Repository:
rL LLVM
https://reviews.llvm.org/D41467
Files:
lib/Transforms/Scalar/NaryReassociate.cpp
test/Transforms/NaryReassociate/pr35710.ll
Index: lib/Transforms/Scalar/NaryReassociate.cpp
===================================================================
--- lib/Transforms/Scalar/NaryReassociate.cpp
+++ lib/Transforms/Scalar/NaryReassociate.cpp
@@ -463,6 +463,12 @@
Instruction *NaryReassociatePass::tryReassociatedBinaryOp(const SCEV *LHSExpr,
Value *RHS,
BinaryOperator *I) {
+ // Need to avoid special case (C1*v)*(C2*v) = 0 because of overflow and
+ // there is Instruction "mul x, 0", as it leads to infinite loop
+ if (I->getOpcode() == Instruction::Mul && LHSExpr->isZero() &&
+ SE->getSCEV(RHS)->isZero())
+ return nullptr;
+
// Look for the closest dominator LHS of I that computes LHSExpr, and replace
// I with LHS op RHS.
auto *LHS = findClosestMatchingDominator(LHSExpr, I);
Index: test/Transforms/NaryReassociate/pr35710.ll
===================================================================
--- test/Transforms/NaryReassociate/pr35710.ll
+++ test/Transforms/NaryReassociate/pr35710.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -nary-reassociate -S | FileCheck %s
+
+; The test check that compilation does not fall into infinite loop.
+
+define i8 @foo(i8 %v) local_unnamed_addr #0 {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT: region.0:
+; CHECK-NEXT: [[TMP0:%.*]] = mul nsw i8 16, [[V:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = mul nsw i8 0, [[TMP0]]
+; CHECK-NEXT: [[TMP2:%.*]] = mul i8 [[TMP1]], [[TMP0]]
+; CHECK-NEXT: ret i8 [[TMP2]]
+;
+region.0:
+ %0 = mul nsw i8 16, %v
+ %1 = mul nsw i8 0, %0
+ %2 = mul nsw i8 1, %1
+ ret i8 %2
+}
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