[llvm] r321218 - [Hexagon] Legalize vector elements to i32 in buildVector32/64

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Wed Dec 20 12:33:49 2017
New Revision: 321218

URL: http://llvm.org/viewvc/llvm-project?rev=321218&view=rev
Log:
[Hexagon] Legalize vector elements to i32 in buildVector32/64

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=321218&r1=321217&r2=321218&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Wed Dec 20 12:33:49 2017
@@ -2524,25 +2524,29 @@ HexagonTargetLowering::buildVector32(Arr
     IsSplat = false;
     break;
   }
-  if (IsSplat)
-    return DAG.getNode(HexagonISD::VSPLAT, dl, VecTy, Elem[First]);
+  if (IsSplat) {
+    // Legalize the operand to VSPLAT.
+    SDValue Ext = DAG.getZExtOrTrunc(Elem[First], dl, MVT::i32);
+    return DAG.getNode(HexagonISD::VSPLAT, dl, VecTy, Ext);
+  }
 
   // Generate
   //   (zxtb(Elem[0]) | (zxtb(Elem[1]) << 8)) |
   //   (zxtb(Elem[2]) | (zxtb(Elem[3]) << 8)) << 16
+  assert(Elem.size() == 4);
+  SDValue Vs[4];
+  for (unsigned i = 0; i != 4; ++i) {
+    Vs[i] = DAG.getZExtOrTrunc(Elem[i], dl, MVT::i32);
+    Vs[i] = DAG.getZeroExtendInReg(Vs[i], dl, MVT::i8);
+  }
   SDValue S8 = DAG.getConstant(8, dl, MVT::i32);
-  SDValue V0 = DAG.getZeroExtendInReg(Elem[0], dl, MVT::i8);
-  SDValue V1 = DAG.getZeroExtendInReg(Elem[1], dl, MVT::i8);
-  SDValue V2 = DAG.getZeroExtendInReg(Elem[2], dl, MVT::i8);
-  SDValue V3 = DAG.getZeroExtendInReg(Elem[3], dl, MVT::i8);
-
-  SDValue V4 = DAG.getNode(ISD::SHL, dl, MVT::i32, {V1, S8});
-  SDValue V5 = DAG.getNode(ISD::SHL, dl, MVT::i32, {V3, S8});
-  SDValue V6 = DAG.getNode(ISD::OR, dl, MVT::i32, {V0, V4});
-  SDValue V7 = DAG.getNode(ISD::OR, dl, MVT::i32, {V2, V5});
+  SDValue T0 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[1], S8});
+  SDValue T1 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[3], S8});
+  SDValue B0 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[0], T0});
+  SDValue B1 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[2], T1});
 
-  SDValue T0 = getNode(Hexagon::A2_combine_ll, dl, MVT::i32, {V7, V6}, DAG);
-  return DAG.getBitcast(MVT::v4i8, T0);
+  SDValue R = getNode(Hexagon::A2_combine_ll, dl, MVT::i32, {B1, B0}, DAG);
+  return DAG.getBitcast(MVT::v4i8, R);
 }
 
 SDValue
@@ -2579,8 +2583,11 @@ HexagonTargetLowering::buildVector64(Arr
       IsSplat = false;
       break;
     }
-    if (IsSplat)
-      return DAG.getNode(HexagonISD::VSPLAT, dl, VecTy, Elem[First]);
+    if (IsSplat) {
+      // Legalize the operand to VSPLAT.
+      SDValue Ext = DAG.getZExtOrTrunc(Elem[First], dl, MVT::i32);
+      return DAG.getNode(HexagonISD::VSPLAT, dl, VecTy, Ext);
+    }
   }
 
   // Then try constant.