[PATCH] D37985: [AMDGPU] add LDS f32 intrinsics

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Dec 20 09:19:29 PST 2017


arsenm added inline comments.


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Comment at: include/llvm/IR/IntrinsicsAMDGPU.td:306
+
+def int_amdgcn_atomic_add : AMDGPUAtomicF32Intrin;
+def int_amdgcn_atomic_min : AMDGPUAtomicF32Intrin;
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These should probably be named fadd.. etc to match the IR operations


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Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:574-576
     Info.vol = !Vol || !Vol->isZero();
     Info.readMem = true;
     Info.writeMem = true;
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This will need to be rebased since I just changed these last week


================
Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:6549-6552
+  case AMDGPUISD::ATOMIC_DEC:
+  case AMDGPUISD::ATOMIC_LOAD_FADD:
+  case AMDGPUISD::ATOMIC_LOAD_FMIN:
+  case AMDGPUISD::ATOMIC_LOAD_FMAX:  // TODO: Target mem intrinsics.
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Tests for these with this combine would be nice


================
Comment at: test/CodeGen/AMDGPU/lds_atomic_f32.ll:1
+; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope %s
+declare float @llvm.amdgcn.atomic.add.f32(float addrspace(3)* nocapture, float, i32, i32, i1)
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Can you also add a pre-gfx9 run line, and check for the m0 initialization


https://reviews.llvm.org/D37985





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