[PATCH] D40554: [PowerPC] Fix bugs in sign-/zero-extension elimination

[Tony Jiang via Phabricator via llvm-commits]

jtony added a comment.

As you mentioned `some registers defined by ORIS/ANDIS/XORIS were identified as already sign-extended. But, it is not true for sign extension depending on the immediate (while it is ok for zero extension). ` Can you provide some details  (maybe in a comment) about  how they depend on the immediate?  This would be helpful for future maintainers.



================
Comment at: lib/Target/PowerPC/PPCInstrInfo.cpp:2164
 // i.e. 0 to 31-th bits are same as 32-th bit.
-static bool isSignExtendingOp(const MachineInstr &MI) {
-  int Opcode = MI.getOpcode();
+static bool definedBySignExtendingOp(const unsigned Reg,
+                                     const MachineRegisterInfo *MRI) {
----------------
We need to update this function  name.


================
Comment at: lib/Target/PowerPC/PPCInstrInfo.cpp:2201
+
+  if (Opcode == PPC::RLDICL && MI->getOperand(3).getImm() >= 33)
     return true;
----------------
Can you put  a comment here to explain why only when the the immediate is great or equal than 33  the value is sign-extended? 


https://reviews.llvm.org/D40554