[PATCH] D41446: [TableGen][AsmMatcherEmitter] Generate assembler checks for tied operands

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
sdesmalen added reviewers: olista01, rengolin, mcrosier, fhahn, craig.topper, evandro, echristo.
Herald added a subscriber: javed.absar.

This extends TableGen's AsmMatcherEmitter with code that generates
a table with tied-operand constraints. The constraints are checked
when parsing the instruction. If an operand is not equal to its tied operand,
the assembler will give an error.

Patch [2/3] in a series to add operand constraint checks for SVE's predicated ADD/SUB.


https://reviews.llvm.org/D41446

Files:
  include/llvm/MC/MCParser/MCTargetAsmParser.h
  lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  utils/TableGen/AsmMatcherEmitter.cpp

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D41446.127709.patch
Type: text/x-patch
Size: 9850 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20171220/75b3f136/attachment.bin>