[PATCH] D41445: [AArch64][AsmParser] Add isScalarReg() and repurpose isReg()

Sander de Smalen via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Dec 20 06:40:39 PST 2017


sdesmalen created this revision.
sdesmalen added reviewers: rengolin, mcrosier, evandro, fhahn, echristo.
Herald added subscribers: kristof.beyls, javed.absar, aemerson.

isReg() in AArch64AsmParser.cpp is a bit of a misnomer, and would be better named 'isScalarReg()' instead.

Patch [1/3] in a series to add operand constraint checks for SVE's predicated ADD/SUB.


https://reviews.llvm.org/D41445

Files:
  lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D41445.127708.patch
Type: text/x-patch
Size: 4619 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20171220/3ca56baa/attachment.bin>


More information about the llvm-commits mailing list