[llvm] r321170 - Trivial commit to force LLVM to run TableGen for Mips target after

[Sander de Smalen via llvm-commits]

Author: s.desmalen
Date: Wed Dec 20 04:45:40 2017
New Revision: 321170

URL: http://llvm.org/viewvc/llvm-project?rev=321170&view=rev
Log:
Trivial commit to force LLVM to run TableGen for Mips target after
a change to the AsmMatcherEmitter, and should fix the buildbot
failure on llvm-clang-x86_64-expensive-checks-win.

The issue is also described here:
http://lists.llvm.org/pipermail/llvm-dev/2017-December/119617.html


Modified:
    llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td

Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=321170&r1=321169&r2=321170&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Wed Dec 20 04:45:40 2017
@@ -38,7 +38,7 @@ class MipsRegWithSubRegs<bits<16> Enc, s
   let Namespace = "Mips";
 }
 
-// Mips CPU Registers
+// Mips CPU Registers.
 class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>;
 
 // Mips 64-bit CPU Registers