[PATCH] D41377: [AMDGPU] Turn off MergeConsecutiveStores() before Instruction Selection for AMDGPU

[Mark Searles via Phabricator via llvm-commits]

msearles created this revision.
msearles added a reviewer: arsenm.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, kzhuravl.

Turn off MergeConsecutiveStores() before Instruction Selection for AMDGPU. Commit dbbb6c5fc3642987430866dffdf710df4f616ac7 turned on MergeConsecutiveStores() before Instruction Selection for all targets. Enough AMDGPU compiles go into an infinite loop ( MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges; MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off until the issues can be addressed.


https://reviews.llvm.org/D41377

Files:
  lib/Target/AMDGPU/AMDGPUISelLowering.h
  test/CodeGen/AMDGPU/amdgpu.private-memory.ll
  test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll


Index: test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll
@@ -0,0 +1,33 @@
+; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -verify-machineinstrs < %s | FileCheck %s
+
+; Effectively, check that the compile finishes.
+; In the case of an infinite loop, llc toggles between merging 2 ST4s
+; ( MergeConsecutiveStores() ) and breaking the resulting ST8 apart
+; ( LegalizeStoreOps() )
+
+; Check that code was generated; we know that there will be
+; a s_endpgm, so check for it.
+
+target datalayout = "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"
+
+; CHECK: s_endpgm
+define weak_odr amdgpu_kernel void @_Z6brokenPd(double* %arg) {
+bb:
+  %tmp = alloca double, align 8, addrspace(5)
+  %tmp1 = alloca double, align 8, addrspace(5)
+  %tmp2 = load double, double* %arg, align 8
+  br i1 1, label %bb43, label %bb32
+
+bb23:                                             ; preds = %bb
+  br label %bb32
+
+bb32:                                             ; preds = %bb23, %bb
+  %tmp37 = phi double addrspace(5)* [ %tmp1, %bb23 ], [ %tmp, %bb ]
+  store double %tmp2, double addrspace(5)* %tmp37, align 8
+  br label %bb43
+
+bb43:                                             ; preds = %bb32, %bb
+  %tmp44 = phi double [ 0x7FF8123000000000, %bb32 ], [ 0x7FF8000000000000, %bb ]
+  store double %tmp44, double* %arg, align 8
+  ret void
+}
Index: test/CodeGen/AMDGPU/amdgpu.private-memory.ll
===================================================================
--- test/CodeGen/AMDGPU/amdgpu.private-memory.ll
+++ test/CodeGen/AMDGPU/amdgpu.private-memory.ll
@@ -251,7 +251,8 @@
 
 ; R600: MOVA_INT
 
-; SI-PROMOTE-DAG: buffer_store_short v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4 ; encoding:
+; SI-PROMOTE-DAG: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4 ; encoding:
+; SI-PROMOTE-DAG: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:5 ; encoding:
 
 ; SI-ALLOCA-DAG: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4 ; encoding: [0x04,0x00,0x60,0xe0
 ; SI-ALLOCA-DAG: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:5 ; encoding: [0x05,0x00,0x60,0xe0
Index: lib/Target/AMDGPU/AMDGPUISelLowering.h
===================================================================
--- lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -202,6 +202,8 @@
 
   const char* getTargetNodeName(unsigned Opcode) const override;
 
+  bool mergeStoresAfterLegalization() const override { return false; }
+
   bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
     return true;
   }


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