[llvm] r321024 - Revert "[AArch64][SVE] Asm" changes, they broke libjpeg_turbo

Reid Kleckner via llvm-commits llvm-commits at lists.llvm.org
Mon Dec 18 12:58:26 PST 2017


Author: rnk
Date: Mon Dec 18 12:58:25 2017
New Revision: 321024

URL: http://llvm.org/viewvc/llvm-project?rev=321024&view=rev
Log:
Revert "[AArch64][SVE] Asm" changes, they broke libjpeg_turbo

This reverts changes r320992, r320986, r320973, and r320970.

r320970 by itself breaks the test case, and the rest depend on it.

Test case will land soon.

Removed:
    llvm/trunk/test/MC/AArch64/SVE/dot-req-diagnostics.s
    llvm/trunk/test/MC/AArch64/SVE/dot-req.s
    llvm/trunk/test/MC/AArch64/SVE/zip1-diagnostics.s
    llvm/trunk/test/MC/AArch64/SVE/zip1.s
    llvm/trunk/test/MC/AArch64/SVE/zip2-diagnostics.s
    llvm/trunk/test/MC/AArch64/SVE/zip2.s
Modified:
    llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td
    llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
    llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
    llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
    llvm/trunk/test/MC/AArch64/SVE/add.s
    llvm/trunk/test/MC/AArch64/SVE/sub.s
    llvm/trunk/test/MC/AArch64/armv8.2a-statistical-profiling.s
    llvm/trunk/test/MC/AArch64/armv8.3a-complex.s
    llvm/trunk/test/MC/AArch64/armv8.3a-rcpc.s
    llvm/trunk/test/MC/Mips/eva/invalid-noeva-wrong-error.s
    llvm/trunk/test/MC/Mips/eva/invalid.s
    llvm/trunk/test/MC/Mips/eva/invalid_R6.s
    llvm/trunk/test/MC/Mips/micromips-dsp/invalid-wrong-error.s
    llvm/trunk/test/MC/Mips/micromips/invalid-wrong-error.s
    llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s
    llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
    llvm/trunk/test/MC/Mips/mips1/invalid-mips2-wrong-error.s
    llvm/trunk/test/MC/Mips/mips1/invalid-mips3-wrong-error.s
    llvm/trunk/test/MC/Mips/mips1/invalid-mips3.s
    llvm/trunk/test/MC/Mips/mips1/invalid-mips4-wrong-error.s
    llvm/trunk/test/MC/Mips/mips1/invalid-mips4.s
    llvm/trunk/test/MC/Mips/mips1/invalid-mips5.s
    llvm/trunk/test/MC/Mips/mips2/invalid-mips3-wrong-error.s
    llvm/trunk/test/MC/Mips/mips2/invalid-mips3.s
    llvm/trunk/test/MC/Mips/mips2/invalid-mips4-wrong-error.s
    llvm/trunk/test/MC/Mips/mips2/invalid-mips4.s
    llvm/trunk/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s
    llvm/trunk/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s
    llvm/trunk/test/MC/Mips/mips32r6/invalid.s
    llvm/trunk/test/MC/Mips/mips64/invalid-mips64r2.s
    llvm/trunk/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s
    llvm/trunk/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s
    llvm/trunk/test/MC/Mips/mips64r6/invalid.s
    llvm/trunk/test/MC/Mips/msa/invalid.s
    llvm/trunk/test/MC/Mips/target-soft-float.s
    llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td Mon Dec 18 12:58:25 2017
@@ -652,24 +652,6 @@ def XSeqPairClassOperand :
 
 //===----- END: v8.1a atomic CASP register operands -----------------------===//
 
-// SVE predicate registers
-def P0    : AArch64Reg<0,   "p0">, DwarfRegNum<[48]>;
-def P1    : AArch64Reg<1,   "p1">, DwarfRegNum<[49]>;
-def P2    : AArch64Reg<2,   "p2">, DwarfRegNum<[50]>;
-def P3    : AArch64Reg<3,   "p3">, DwarfRegNum<[51]>;
-def P4    : AArch64Reg<4,   "p4">, DwarfRegNum<[52]>;
-def P5    : AArch64Reg<5,   "p5">, DwarfRegNum<[53]>;
-def P6    : AArch64Reg<6,   "p6">, DwarfRegNum<[54]>;
-def P7    : AArch64Reg<7,   "p7">, DwarfRegNum<[55]>;
-def P8    : AArch64Reg<8,   "p8">, DwarfRegNum<[56]>;
-def P9    : AArch64Reg<9,   "p9">, DwarfRegNum<[57]>;
-def P10   : AArch64Reg<10, "p10">, DwarfRegNum<[58]>;
-def P11   : AArch64Reg<11, "p11">, DwarfRegNum<[59]>;
-def P12   : AArch64Reg<12, "p12">, DwarfRegNum<[60]>;
-def P13   : AArch64Reg<13, "p13">, DwarfRegNum<[61]>;
-def P14   : AArch64Reg<14, "p14">, DwarfRegNum<[62]>;
-def P15   : AArch64Reg<15, "p15">, DwarfRegNum<[63]>;
-
 // The part of SVE registers that don't overlap Neon registers.
 // These are only used as part of clobber lists.
 def Z0_HI    : AArch64Reg<0,   "z0_hi">;
@@ -749,43 +731,11 @@ class SVERegOp <string Suffix, AsmOperan
   let ParserMatchClass = C;
 }
 
-class PPRRegOp <string Suffix, AsmOperandClass C,
-                RegisterClass RC> : SVERegOp<Suffix, C, RC> {}
 class ZPRRegOp <string Suffix, AsmOperandClass C,
                 RegisterClass RC> : SVERegOp<Suffix, C, RC> {}
 
 //******************************************************************************
 
-// SVE predicate register class.
-def PPR : RegisterClass<"AArch64",
-                        [nxv16i1, nxv8i1, nxv4i1, nxv2i1],
-                        16, (sequence "P%u", 0, 15)> {
-  let Size = 16;
-}
-
-class PPRAsmOperand <string name, int Width>: AsmOperandClass {
-  let Name = "SVE" # name # "Reg";
-  let PredicateMethod = "isSVEVectorRegOfWidth<"
-                            # Width # ", AArch64::PPRRegClassID>";
-  let DiagnosticType = "InvalidSVE" # name # "Reg";
-  let RenderMethod = "addRegOperands";
-  let ParserMethod = "tryParseSVEPredicateVector";
-}
-
-def PPRAsmOpAny : PPRAsmOperand<"PredicateAny", -1>;
-def PPRAsmOp8   : PPRAsmOperand<"PredicateB",  8>;
-def PPRAsmOp16  : PPRAsmOperand<"PredicateH", 16>;
-def PPRAsmOp32  : PPRAsmOperand<"PredicateS", 32>;
-def PPRAsmOp64  : PPRAsmOperand<"PredicateD", 64>;
-
-def PPRAny : PPRRegOp<"",  PPRAsmOpAny, PPR>;
-def PPR8   : PPRRegOp<"b", PPRAsmOp8,   PPR>;
-def PPR16  : PPRRegOp<"h", PPRAsmOp16,  PPR>;
-def PPR32  : PPRRegOp<"s", PPRAsmOp32,  PPR>;
-def PPR64  : PPRRegOp<"d", PPRAsmOp64,  PPR>;
-
-//******************************************************************************
-
 // SVE vector register class
 def ZPR : RegisterClass<"AArch64",
                         [nxv16i8, nxv8i16, nxv4i32, nxv2i64,
@@ -798,8 +748,7 @@ def ZPR : RegisterClass<"AArch64",
 
 class ZPRAsmOperand <string name, int Width>: AsmOperandClass {
   let Name = "SVE" # name # "Reg";
-  let PredicateMethod = "isSVEVectorRegOfWidth<"
-                            # Width # ", AArch64::ZPRRegClassID>";
+  let PredicateMethod = "isSVEDataVectorRegOfWidth<" # Width # ">";
   let RenderMethod = "addRegOperands";
   let ParserMethod = "tryParseSVEDataVector<"
                                # !if(!eq(Width, -1), "false", "true") # ">";

Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Mon Dec 18 12:58:25 2017
@@ -14,10 +14,4 @@
 let Predicates = [HasSVE] in {
   defm ADD_ZZZ   : sve_int_bin_cons_arit_0<0b000, "add">;
   defm SUB_ZZZ   : sve_int_bin_cons_arit_0<0b001, "sub">;
-
-  defm ZIP1_ZZZ : sve_int_perm_bin_perm_zz<0b000, "zip1">;
-  defm ZIP2_ZZZ : sve_int_perm_bin_perm_zz<0b001, "zip2">;
-
-  defm ZIP1_PPP : sve_int_perm_bin_perm_pp<0b000, "zip1">;
-  defm ZIP2_PPP : sve_int_perm_bin_perm_pp<0b001, "zip2">;
 }

Modified: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp Mon Dec 18 12:58:25 2017
@@ -59,12 +59,7 @@ using namespace llvm;
 
 namespace {
 
-enum class RegKind {
-  Scalar,
-  NeonVector,
-  SVEDataVector,
-  SVEPredicateVector
-};
+enum class RegKind {Scalar, NeonVector, SVEDataVector};
 
 class AArch64AsmParser : public MCTargetAsmParser {
 private:
@@ -139,7 +134,6 @@ private:
   OperandMatchResultTy tryParseGPRSeqPair(OperandVector &Operands);
   template <bool ParseSuffix>
   OperandMatchResultTy tryParseSVEDataVector(OperandVector &Operands);
-  OperandMatchResultTy tryParseSVEPredicateVector(OperandVector &Operands);
 
 public:
   enum AArch64MatchResultTy {
@@ -832,26 +826,14 @@ public:
                Reg.RegNum);
   }
 
-  template <unsigned Class> bool isSVEVectorReg() const {
-    RegKind RK;
-    switch (Class) {
-    case AArch64::ZPRRegClassID:
-      RK = RegKind::SVEDataVector;
-      break;
-    case AArch64::PPRRegClassID:
-      RK = RegKind::SVEPredicateVector;
-      break;
-    default:
-      llvm_unreachable("Unsupport register class");
-    }
-
-    return (Kind == k_Register && Reg.Kind == RK) &&
+  template <unsigned Class = AArch64::ZPRRegClassID>
+  bool isSVEDataVectorReg() const {
+    return (Kind == k_Register && Reg.Kind == RegKind::SVEDataVector) &&
            AArch64MCRegisterClasses[Class].contains(getReg());
   }
 
-  template <int ElementWidth, unsigned Class>
-  bool isSVEVectorRegOfWidth() const {
-    return isSVEVectorReg<Class>() &&
+  template <int ElementWidth> bool isSVEDataVectorRegOfWidth() const {
+    return isSVEDataVectorReg() &&
            (ElementWidth == -1 || Reg.ElementWidth == ElementWidth);
   }
 
@@ -1944,27 +1926,6 @@ static unsigned matchSVEDataVectorRegNam
       .Default(0);
 }
 
-static unsigned matchSVEPredicateVectorRegName(StringRef Name) {
-  return StringSwitch<unsigned>(Name.lower())
-      .Case("p0", AArch64::P0)
-      .Case("p1", AArch64::P1)
-      .Case("p2", AArch64::P2)
-      .Case("p3", AArch64::P3)
-      .Case("p4", AArch64::P4)
-      .Case("p5", AArch64::P5)
-      .Case("p6", AArch64::P6)
-      .Case("p7", AArch64::P7)
-      .Case("p8", AArch64::P8)
-      .Case("p9", AArch64::P9)
-      .Case("p10", AArch64::P10)
-      .Case("p11", AArch64::P11)
-      .Case("p12", AArch64::P12)
-      .Case("p13", AArch64::P13)
-      .Case("p14", AArch64::P14)
-      .Case("p15", AArch64::P15)
-      .Default(0);
-}
-
 static bool isValidSVEKind(StringRef Name) {
   return StringSwitch<bool>(Name.lower())
       .Case(".b", true)
@@ -1975,8 +1936,8 @@ static bool isValidSVEKind(StringRef Nam
       .Default(false);
 }
 
-static bool isSVERegister(StringRef Name) {
-  return Name[0] == 'z' || Name[0] == 'p';
+static bool isSVEDataVectorRegister(StringRef Name) {
+  return Name[0] == 'z';
 }
 
 static void parseValidVectorKind(StringRef Name, unsigned &NumElements,
@@ -2019,9 +1980,6 @@ unsigned AArch64AsmParser::matchRegister
   case RegKind::SVEDataVector:
     RegNum = matchSVEDataVectorRegName(Name);
     break;
-  case RegKind::SVEPredicateVector:
-    RegNum = matchSVEPredicateVectorRegName(Name);
-    break;
   }
 
   if (!RegNum) {
@@ -2049,7 +2007,7 @@ int AArch64AsmParser::tryParseRegister()
     return -1;
 
   std::string lowerCase = Tok.getString().lower();
-  if (isSVERegister(lowerCase))
+  if (isSVEDataVectorRegister(lowerCase))
     return -1;
 
   unsigned RegNum = matchRegisterNameAlias(lowerCase, RegKind::Scalar);
@@ -2784,36 +2742,6 @@ AArch64AsmParser::tryParseSVERegister(in
   return MatchOperand_NoMatch;
 }
 
-/// tryParseSVEPredicateVector - Parse a SVE predicate register operand.
-OperandMatchResultTy
-AArch64AsmParser::tryParseSVEPredicateVector(OperandVector &Operands) {
-  // Check for a SVE predicate register specifier first.
-  const SMLoc S = getLoc();
-  StringRef Kind;
-  int RegNum = -1;
-  auto Res = tryParseSVERegister(RegNum, Kind, RegKind::SVEPredicateVector);
-  if (Res != MatchOperand_Success)
-    return Res;
-
-  unsigned ElementWidth = StringSwitch<unsigned>(Kind.lower())
-                              .Case("", -1)
-                              .Case(".b", 8)
-                              .Case(".h", 16)
-                              .Case(".s", 32)
-                              .Case(".d", 64)
-                              .Case(".q", 128)
-                              .Default(0);
-
-  if (!ElementWidth)
-    return MatchOperand_NoMatch;
-
-  Operands.push_back(
-      AArch64Operand::CreateReg(RegNum, RegKind::SVEPredicateVector,
-                                ElementWidth, S, getLoc(), getContext()));
-
-  return MatchOperand_Success;
-}
-
 /// parseRegister - Parse a non-vector register operand.
 bool AArch64AsmParser::parseRegister(OperandVector &Operands) {
   SMLoc S = getLoc();
@@ -3034,12 +2962,9 @@ AArch64AsmParser::tryParseGPR64sp0Operan
 bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
                                   bool invertCondCode) {
   MCAsmParser &Parser = getParser();
-
-  OperandMatchResultTy ResTy =
-      MatchOperandParserImpl(Operands, Mnemonic, /*ParseForAllFeatures=*/ true);
-
   // Check if the current operand has a custom associated parser, if so, try to
   // custom parse the operand, or fallback to the general approach.
+  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
   if (ResTy == MatchOperand_Success)
     return false;
   // If there wasn't a custom match, try the generic matcher below. Otherwise,
@@ -3650,12 +3575,6 @@ bool AArch64AsmParser::showMatchError(SM
         ComputeAvailableFeatures(STI->getFeatureBits()));
     return Error(Loc, "unrecognized instruction mnemonic" + Suggestion);
   }
-  case Match_InvalidSVEPredicateAnyReg:
-  case Match_InvalidSVEPredicateBReg:
-  case Match_InvalidSVEPredicateHReg:
-  case Match_InvalidSVEPredicateSReg:
-  case Match_InvalidSVEPredicateDReg:
-    return Error(Loc, "invalid predicate register.");
   default:
     llvm_unreachable("unexpected error code!");
   }
@@ -4080,11 +3999,6 @@ bool AArch64AsmParser::MatchAndEmitInstr
   case Match_InvalidLabel:
   case Match_InvalidComplexRotationEven:
   case Match_InvalidComplexRotationOdd:
-  case Match_InvalidSVEPredicateAnyReg:
-  case Match_InvalidSVEPredicateBReg:
-  case Match_InvalidSVEPredicateHReg:
-  case Match_InvalidSVEPredicateSReg:
-  case Match_InvalidSVEPredicateDReg:
   case Match_MSR:
   case Match_MRS: {
     if (ErrorInfo >= Operands.size())
@@ -4435,20 +4349,6 @@ bool AArch64AsmParser::parseDirectiveReq
                    "sve vector register without type specifier expected");
   }
 
-  if (RegNum == -1) {
-    StringRef Kind;
-    RegisterKind = RegKind::SVEPredicateVector;
-    OperandMatchResultTy Res =
-        tryParseSVERegister(RegNum, Kind, RegKind::SVEPredicateVector);
-
-    if (Res == MatchOperand_ParseFail)
-      return true;
-
-    if (Res == MatchOperand_Success && !Kind.empty())
-      return Error(SRegLoc,
-                   "sve predicate register without type specifier expected");
-  }
-
   if (RegNum == -1)
     return Error(SRegLoc, "register name or alias expected");
 

Modified: llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp Mon Dec 18 12:58:25 2017
@@ -88,9 +88,6 @@ static DecodeStatus DecodeDDDDRegisterCl
 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
                                            const void *Decode);
-static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
-                                           uint64_t Address,
-                                           const void *Decode);
 
 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
                                                uint64_t Address,
@@ -463,23 +460,6 @@ static DecodeStatus DecodeZPRRegisterCla
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
-
-static const unsigned PPRDecoderTable[] = {
-  AArch64::P0,  AArch64::P1,  AArch64::P2,  AArch64::P3,
-  AArch64::P4,  AArch64::P5,  AArch64::P6,  AArch64::P7,
-  AArch64::P8,  AArch64::P9,  AArch64::P10, AArch64::P11,
-  AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15
-};
-
-static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
-                                           uint64_t Addr, const void *Decoder) {
-  if (RegNo > 15)
-    return Fail;
-
-  unsigned Register = PPRDecoderTable[RegNo];
-  Inst.addOperand(MCOperand::createReg(Register));
-  return Success;
-}
 
 static const unsigned VectorDecoderTable[] = {
     AArch64::Q0,  AArch64::Q1,  AArch64::Q2,  AArch64::Q3,  AArch64::Q4,

Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Mon Dec 18 12:58:25 2017
@@ -39,65 +39,3 @@ multiclass sve_int_bin_cons_arit_0<bits<
   def _S : sve_int_bin_cons_arit_0<0b10, opc, asm, ZPR32>;
   def _D : sve_int_bin_cons_arit_0<0b11, opc, asm, ZPR64>;
 }
-
-//===----------------------------------------------------------------------===//
-// SVE Permute - In Lane Group
-//===----------------------------------------------------------------------===//
-
-class sve_int_perm_bin_perm_zz<bits<3> opc, bits<2> sz8_64, string asm,
-                               ZPRRegOp zprty>
-: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
-  asm, "\t$Zd, $Zn, $Zm",
-  "",
-  []>, Sched<[]> {
-  bits<5> Zd;
-  bits<5> Zm;
-  bits<5> Zn;
-  let Inst{31-24} = 0b00000101;
-  let Inst{23-22} = sz8_64;
-  let Inst{21}    = 0b1;
-  let Inst{20-16} = Zm;
-  let Inst{15-13} = 0b011;
-  let Inst{12-10} = opc;
-  let Inst{9-5}   = Zn;
-  let Inst{4-0}   = Zd;
-}
-
-multiclass sve_int_perm_bin_perm_zz<bits<3> opc, string asm> {
-  def _B : sve_int_perm_bin_perm_zz<opc, 0b00, asm, ZPR8>;
-  def _H : sve_int_perm_bin_perm_zz<opc, 0b01, asm, ZPR16>;
-  def _S : sve_int_perm_bin_perm_zz<opc, 0b10, asm, ZPR32>;
-  def _D : sve_int_perm_bin_perm_zz<opc, 0b11, asm, ZPR64>;
-}
-
-//===----------------------------------------------------------------------===//
-// SVE Permute - Predicates Group
-//===----------------------------------------------------------------------===//
-
-class sve_int_perm_bin_perm_pp<bits<3> opc, bits<2> sz8_64, string asm,
-                               PPRRegOp pprty>
-: I<(outs pprty:$Pd), (ins pprty:$Pn, pprty:$Pm),
-  asm, "\t$Pd, $Pn, $Pm",
-  "",
-  []>, Sched<[]> {
-  bits<4> Pd;
-  bits<4> Pm;
-  bits<4> Pn;
-  let Inst{31-24} = 0b00000101;
-  let Inst{23-22} = sz8_64;
-  let Inst{21-20} = 0b10;
-  let Inst{19-16} = Pm;
-  let Inst{15-13} = 0b010;
-  let Inst{12-10} = opc;
-  let Inst{9}     = 0b0;
-  let Inst{8-5}   = Pn;
-  let Inst{4}     = 0b0;
-  let Inst{3-0}   = Pd;
-}
-
-multiclass sve_int_perm_bin_perm_pp<bits<3> opc, string asm> {
-  def _B : sve_int_perm_bin_perm_pp<opc, 0b00, asm, PPR8>;
-  def _H : sve_int_perm_bin_perm_pp<opc, 0b01, asm, PPR16>;
-  def _S : sve_int_perm_bin_perm_pp<opc, 0b10, asm, PPR32>;
-  def _D : sve_int_perm_bin_perm_pp<opc, 0b11, asm, PPR64>;
-}
\ No newline at end of file

Modified: llvm/trunk/test/MC/AArch64/SVE/add.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/add.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/add.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/add.s Mon Dec 18 12:58:25 2017
@@ -10,95 +10,95 @@
 add     z31.s, z31.s, z31.s
 // CHECK-INST: add     z31.s, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x03,0xbf,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ff 03 bf 04 <unknown>
 
 add     z23.d, z13.d, z8.d
 // CHECK-INST: add     z23.d, z13.d, z8.d
 // CHECK-ENCODING: [0xb7,0x01,0xe8,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: b7 01 e8 04 <unknown>
 
 add     z0.s, z0.s, z0.s
 // CHECK-INST: add     z0.s, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x00,0xa0,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 00 a0 04 <unknown>
 
 add     z31.d, z31.d, z31.d
 // CHECK-INST: add     z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x03,0xff,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ff 03 ff 04 <unknown>
 
 add     z21.b, z10.b, z21.b
 // CHECK-INST: add     z21.b, z10.b, z21.b
 // CHECK-ENCODING: [0x55,0x01,0x35,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 55 01 35 04 <unknown>
 
 add     z31.b, z31.b, z31.b
 // CHECK-INST: add     z31.b, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x03,0x3f,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ff 03 3f 04 <unknown>
 
 add     z0.h, z0.h, z0.h
 // CHECK-INST: add     z0.h, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x00,0x60,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 00 60 04 <unknown>
 
 add     z23.b, z13.b, z8.b
 // CHECK-INST: add     z23.b, z13.b, z8.b
 // CHECK-ENCODING: [0xb7,0x01,0x28,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: b7 01 28 04 <unknown>
 
 add     z0.d, z0.d, z0.d
 // CHECK-INST: add     z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x00,0xe0,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 00 e0 04 <unknown>
 
 add     z31.h, z31.h, z31.h
 // CHECK-INST: add     z31.h, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x03,0x7f,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ff 03 7f 04 <unknown>
 
 add     z0.b, z0.b, z0.b
 // CHECK-INST: add     z0.b, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x00,0x20,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 00 20 04 <unknown>
 
 add     z21.d, z10.d, z21.d
 // CHECK-INST: add     z21.d, z10.d, z21.d
 // CHECK-ENCODING: [0x55,0x01,0xf5,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 55 01 f5 04 <unknown>
 
 add     z21.h, z10.h, z21.h
 // CHECK-INST: add     z21.h, z10.h, z21.h
 // CHECK-ENCODING: [0x55,0x01,0x75,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 55 01 75 04 <unknown>
 
 add     z21.s, z10.s, z21.s
 // CHECK-INST: add     z21.s, z10.s, z21.s
 // CHECK-ENCODING: [0x55,0x01,0xb5,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 55 01 b5 04 <unknown>
 
 add     z23.h, z13.h, z8.h
 // CHECK-INST: add     z23.h, z13.h, z8.h
 // CHECK-ENCODING: [0xb7,0x01,0x68,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: b7 01 68 04 <unknown>
 
 add     z23.s, z13.s, z8.s
 // CHECK-INST: add     z23.s, z13.s, z8.s
 // CHECK-ENCODING: [0xb7,0x01,0xa8,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: b7 01 a8 04 <unknown>

Removed: llvm/trunk/test/MC/AArch64/SVE/dot-req-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/dot-req-diagnostics.s?rev=321023&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/dot-req-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/dot-req-diagnostics.s (removed)
@@ -1,20 +0,0 @@
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+sve < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-ERROR %s
-
-foo:
-// CHECK: error: sve predicate register without type specifier expected
-  pbarb .req p1.b
-// CHECK: error: sve predicate register without type specifier expected
-  pbarh .req p1.h
-// CHECK: error: sve predicate register without type specifier expected
-  pbars .req p1.s
-// CHECK: error: sve predicate register without type specifier expected
-  pbard .req p1.d
-
-// CHECK: error: sve vector register without type specifier expected
-  zbarb .req z1.b
-// CHECK: error: sve vector register without type specifier expected
-  zbarh .req z1.h
-// CHECK: error: sve vector register without type specifier expected
-  zbars .req z1.s
-// CHECK: error: sve vector register without type specifier expected
-  zbard .req z1.d

Removed: llvm/trunk/test/MC/AArch64/SVE/dot-req.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/dot-req.s?rev=321023&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/dot-req.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/dot-req.s (removed)
@@ -1,9 +0,0 @@
-// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+sve -show-encoding < %s 2>&1 | FileCheck %s
-
-foo:
-// CHECK-NOT: error:
-  pbar .req p1
-
-// CHECK: add z0.s, z1.s, z2.s
-  zbar .req z1
-  add  z0.s, zbar.s, z2.s

Modified: llvm/trunk/test/MC/AArch64/SVE/sub.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sub.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sub.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/sub.s Mon Dec 18 12:58:25 2017
@@ -10,95 +10,95 @@
 sub     z0.h, z0.h, z0.h
 // CHECK-INST: sub     z0.h, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x04,0x60,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 04 60 04 <unknown>
 
 sub     z21.b, z10.b, z21.b
 // CHECK-INST: sub     z21.b, z10.b, z21.b
 // CHECK-ENCODING: [0x55,0x05,0x35,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 55 05 35 04 <unknown>
 
 sub     z31.h, z31.h, z31.h
 // CHECK-INST: sub     z31.h, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x07,0x7f,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ff 07 7f 04 <unknown>
 
 sub     z21.h, z10.h, z21.h
 // CHECK-INST: sub     z21.h, z10.h, z21.h
 // CHECK-ENCODING: [0x55,0x05,0x75,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 55 05 75 04 <unknown>
 
 sub     z31.b, z31.b, z31.b
 // CHECK-INST: sub     z31.b, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x07,0x3f,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ff 07 3f 04 <unknown>
 
 sub     z0.s, z0.s, z0.s
 // CHECK-INST: sub     z0.s, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x04,0xa0,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 04 a0 04 <unknown>
 
 sub     z23.b, z13.b, z8.b
 // CHECK-INST: sub     z23.b, z13.b, z8.b
 // CHECK-ENCODING: [0xb7,0x05,0x28,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: b7 05 28 04 <unknown>
 
 sub     z21.d, z10.d, z21.d
 // CHECK-INST: sub     z21.d, z10.d, z21.d
 // CHECK-ENCODING: [0x55,0x05,0xf5,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 55 05 f5 04 <unknown>
 
 sub     z21.s, z10.s, z21.s
 // CHECK-INST: sub     z21.s, z10.s, z21.s
 // CHECK-ENCODING: [0x55,0x05,0xb5,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 55 05 b5 04 <unknown>
 
 sub     z0.b, z0.b, z0.b
 // CHECK-INST: sub     z0.b, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x04,0x20,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 04 20 04 <unknown>
 
 sub     z23.d, z13.d, z8.d
 // CHECK-INST: sub     z23.d, z13.d, z8.d
 // CHECK-ENCODING: [0xb7,0x05,0xe8,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: b7 05 e8 04 <unknown>
 
 sub     z23.s, z13.s, z8.s
 // CHECK-INST: sub     z23.s, z13.s, z8.s
 // CHECK-ENCODING: [0xb7,0x05,0xa8,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: b7 05 a8 04 <unknown>
 
 sub     z31.d, z31.d, z31.d
 // CHECK-INST: sub     z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x07,0xff,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ff 07 ff 04 <unknown>
 
 sub     z23.h, z13.h, z8.h
 // CHECK-INST: sub     z23.h, z13.h, z8.h
 // CHECK-ENCODING: [0xb7,0x05,0x68,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: b7 05 68 04 <unknown>
 
 sub     z0.d, z0.d, z0.d
 // CHECK-INST: sub     z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x04,0xe0,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 04 e0 04 <unknown>
 
 sub     z31.s, z31.s, z31.s
 // CHECK-INST: sub     z31.s, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x07,0xbf,0x04]
-// CHECK-ERROR: instruction requires: sve
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ff 07 bf 04 <unknown>

Removed: llvm/trunk/test/MC/AArch64/SVE/zip1-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/zip1-diagnostics.s?rev=321023&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/zip1-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/zip1-diagnostics.s (removed)
@@ -1,43 +0,0 @@
-// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
-
-// Invalid element kind.
-zip1 z10.h, z22.h, z31.x
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid sve vector kind qualifier
-// CHECK-NEXT: zip1 z10.h, z22.h, z31.x
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
-// Element size specifiers should match.
-zip1 z10.h, z3.h, z15.b
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
-// CHECK-NEXT: zip1 z10.h, z3.h, z15.b
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
-// Too few operands
-zip1 z1.h, z2.h
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
-// CHECK-NEXT: zip1 z1.h, z2.h
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
-// z32 is not a valid SVE data register
-zip1 z1.s, z2.s, z32.s
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: zip1 z1.s, z2.s, z32.s
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
-// p16 is not a valid SVE predicate register
-zip1 p1.s, p2.s, p16.s
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
-// CHECK-NEXT: zip1 p1.s, p2.s, p16.s
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
-// Combining data and predicate registers as operands
-zip1 z1.s, z2.s, p3.s
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: zip1 z1.s, z2.s, p3.s
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
-// Combining predicate and data registers as operands
-zip1 p1.s, p2.s, z3.s
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
-// CHECK-NEXT: zip1 p1.s, p2.s, z3.s
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

Removed: llvm/trunk/test/MC/AArch64/SVE/zip1.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/zip1.s?rev=321023&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/zip1.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/zip1.s (removed)
@@ -1,104 +0,0 @@
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
-// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
-// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
-// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
-
-zip1    z0.b, z0.b, z0.b
-// CHECK-INST: zip1    z0.b, z0.b, z0.b
-// CHECK-ENCODING: [0x00,0x60,0x20,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 20 05 <unknown>
-
-zip1    z0.h, z0.h, z0.h
-// CHECK-INST: zip1    z0.h, z0.h, z0.h
-// CHECK-ENCODING: [0x00,0x60,0x60,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 60 05 <unknown>
-
-zip1    z0.s, z0.s, z0.s
-// CHECK-INST: zip1    z0.s, z0.s, z0.s
-// CHECK-ENCODING: [0x00,0x60,0xa0,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 a0 05 <unknown>
-
-zip1    z0.d, z0.d, z0.d
-// CHECK-INST: zip1    z0.d, z0.d, z0.d
-// CHECK-ENCODING: [0x00,0x60,0xe0,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 e0 05 <unknown>
-
-zip1    z31.b, z31.b, z31.b
-// CHECK-INST: zip1    z31.b, z31.b, z31.b
-// CHECK-ENCODING: [0xff,0x63,0x3f,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 63 3f 05 <unknown>
-
-zip1    z31.h, z31.h, z31.h
-// CHECK-INST: zip1    z31.h, z31.h, z31.h
-// CHECK-ENCODING: [0xff,0x63,0x7f,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 63 7f 05 <unknown>
-
-zip1    z31.s, z31.s, z31.s
-// CHECK-INST: zip1    z31.s, z31.s, z31.s
-// CHECK-ENCODING: [0xff,0x63,0xbf,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 63 bf 05 <unknown>
-
-zip1    z31.d, z31.d, z31.d
-// CHECK-INST: zip1    z31.d, z31.d, z31.d
-// CHECK-ENCODING: [0xff,0x63,0xff,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 63 ff 05 <unknown>
-
-zip1    p0.b, p0.b, p0.b
-// CHECK-INST: zip1    p0.b, p0.b, p0.b
-// CHECK-ENCODING: [0x00,0x40,0x20,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 40 20 05 <unknown>
-
-zip1    p0.h, p0.h, p0.h
-// CHECK-INST: zip1    p0.h, p0.h, p0.h
-// CHECK-ENCODING: [0x00,0x40,0x60,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 40 60 05 <unknown>
-
-zip1    p0.s, p0.s, p0.s
-// CHECK-INST: zip1    p0.s, p0.s, p0.s
-// CHECK-ENCODING: [0x00,0x40,0xa0,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 40 a0 05 <unknown>
-
-zip1    p0.d, p0.d, p0.d
-// CHECK-INST: zip1    p0.d, p0.d, p0.d
-// CHECK-ENCODING: [0x00,0x40,0xe0,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 40 e0 05 <unknown>
-
-zip1    p15.b, p15.b, p15.b
-// CHECK-INST: zip1    p15.b, p15.b, p15.b
-// CHECK-ENCODING: [0xef,0x41,0x2f,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ef 41 2f 05 <unknown>
-
-zip1    p15.s, p15.s, p15.s
-// CHECK-INST: zip1    p15.s, p15.s, p15.s
-// CHECK-ENCODING: [0xef,0x41,0xaf,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ef 41 af 05 <unknown>
-
-zip1    p15.h, p15.h, p15.h
-// CHECK-INST: zip1    p15.h, p15.h, p15.h
-// CHECK-ENCODING: [0xef,0x41,0x6f,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ef 41 6f 05 <unknown>
-
-zip1    p15.d, p15.d, p15.d
-// CHECK-INST: zip1    p15.d, p15.d, p15.d
-// CHECK-ENCODING: [0xef,0x41,0xef,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ef 41 ef 05 <unknown>

Removed: llvm/trunk/test/MC/AArch64/SVE/zip2-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/zip2-diagnostics.s?rev=321023&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/zip2-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/zip2-diagnostics.s (removed)
@@ -1,43 +0,0 @@
-// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
-
-// Invalid element kind.
-zip2 z6.h, z23.h, z31.x
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid sve vector kind qualifier
-// CHECK-NEXT: zip2 z6.h, z23.h, z31.x
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
-// Element size specifiers should match.
-zip2 z0.h, z30.h, z24.b
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
-// CHECK-NEXT: zip2 z0.h, z30.h, z24.b
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
-// Too few operands
-zip2 z1.h, z2.h
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
-// CHECK-NEXT: zip2 z1.h, z2.h
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
-// z32 is not a valid SVE data register
-zip2 z1.s, z2.s, z32.s
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: zip2 z1.s, z2.s, z32.s
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
-// p16 is not a valid SVE predicate register
-zip2 p1.s, p2.s, p16.s
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
-// CHECK-NEXT: zip2 p1.s, p2.s, p16.s
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
-// Combining data and predicate registers as operands
-zip2 z1.s, z2.s, p3.s
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: zip2 z1.s, z2.s, p3.s
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
-// Combining predicate and data registers as operands
-zip2 p1.s, p2.s, z3.s
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
-// CHECK-NEXT: zip2 p1.s, p2.s, z3.s
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

Removed: llvm/trunk/test/MC/AArch64/SVE/zip2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/zip2.s?rev=321023&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/zip2.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/zip2.s (removed)
@@ -1,104 +0,0 @@
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
-// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
-// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
-// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
-
-zip2    z0.b, z0.b, z0.b
-// CHECK-INST: zip2    z0.b, z0.b, z0.b
-// CHECK-ENCODING: [0x00,0x64,0x20,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 64 20 05 <unknown>
-
-zip2    z0.h, z0.h, z0.h
-// CHECK-INST: zip2    z0.h, z0.h, z0.h
-// CHECK-ENCODING: [0x00,0x64,0x60,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 64 60 05 <unknown>
-
-zip2    z0.s, z0.s, z0.s
-// CHECK-INST: zip2    z0.s, z0.s, z0.s
-// CHECK-ENCODING: [0x00,0x64,0xa0,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 64 a0 05 <unknown>
-
-zip2    z0.d, z0.d, z0.d
-// CHECK-INST: zip2    z0.d, z0.d, z0.d
-// CHECK-ENCODING: [0x00,0x64,0xe0,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 64 e0 05 <unknown>
-
-zip2    z31.b, z31.b, z31.b
-// CHECK-INST: zip2    z31.b, z31.b, z31.b
-// CHECK-ENCODING: [0xff,0x67,0x3f,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 67 3f 05 <unknown>
-
-zip2    z31.h, z31.h, z31.h
-// CHECK-INST: zip2    z31.h, z31.h, z31.h
-// CHECK-ENCODING: [0xff,0x67,0x7f,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 67 7f 05 <unknown>
-
-zip2    z31.s, z31.s, z31.s
-// CHECK-INST: zip2    z31.s, z31.s, z31.s
-// CHECK-ENCODING: [0xff,0x67,0xbf,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 67 bf 05 <unknown>
-
-zip2    z31.d, z31.d, z31.d
-// CHECK-INST: zip2    z31.d, z31.d, z31.d
-// CHECK-ENCODING: [0xff,0x67,0xff,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 67 ff 05 <unknown>
-
-zip2    p0.b, p0.b, p0.b
-// CHECK-INST: zip2    p0.b, p0.b, p0.b
-// CHECK-ENCODING: [0x00,0x44,0x20,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 44 20 05 <unknown>
-
-zip2    p0.h, p0.h, p0.h
-// CHECK-INST: zip2    p0.h, p0.h, p0.h
-// CHECK-ENCODING: [0x00,0x44,0x60,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 44 60 05 <unknown>
-
-zip2    p0.s, p0.s, p0.s
-// CHECK-INST: zip2    p0.s, p0.s, p0.s
-// CHECK-ENCODING: [0x00,0x44,0xa0,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 44 a0 05 <unknown>
-
-zip2    p0.d, p0.d, p0.d
-// CHECK-INST: zip2    p0.d, p0.d, p0.d
-// CHECK-ENCODING: [0x00,0x44,0xe0,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 44 e0 05 <unknown>
-
-zip2    p15.b, p15.b, p15.b
-// CHECK-INST: zip2    p15.b, p15.b, p15.b
-// CHECK-ENCODING: [0xef,0x45,0x2f,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ef 45 2f 05 <unknown>
-
-zip2    p15.h, p15.h, p15.h
-// CHECK-INST: zip2    p15.h, p15.h, p15.h
-// CHECK-ENCODING: [0xef,0x45,0x6f,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ef 45 6f 05 <unknown>
-
-zip2    p15.s, p15.s, p15.s
-// CHECK-INST: zip2    p15.s, p15.s, p15.s
-// CHECK-ENCODING: [0xef,0x45,0xaf,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ef 45 af 05 <unknown>
-
-zip2    p15.d, p15.d, p15.d
-// CHECK-INST: zip2    p15.d, p15.d, p15.d
-// CHECK-ENCODING: [0xef,0x45,0xef,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ef 45 ef 05 <unknown>

Modified: llvm/trunk/test/MC/AArch64/armv8.2a-statistical-profiling.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.2a-statistical-profiling.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.2a-statistical-profiling.s (original)
+++ llvm/trunk/test/MC/AArch64/armv8.2a-statistical-profiling.s Mon Dec 18 12:58:25 2017
@@ -3,7 +3,7 @@
 
   psb csync
 // CHECK: psb csync              // encoding: [0x3f,0x22,0x03,0xd5]
-// NO_SPE:  instruction requires: spe
+// NO_SPE:  invalid operand for instruction
 
   msr pmblimitr_el1, x0
   msr pmbptr_el1, x0

Modified: llvm/trunk/test/MC/AArch64/armv8.3a-complex.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.3a-complex.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.3a-complex.s (original)
+++ llvm/trunk/test/MC/AArch64/armv8.3a-complex.s Mon Dec 18 12:58:25 2017
@@ -133,11 +133,9 @@
 
 // Invalid indices
   fcmla v0.4h, v1.4h, v2.h[2], #0
-// STDERR-NO-FP16: :[[@LINE-1]]:{{[0-9]*}}: error: invalid operand for instruction
-// STDERR-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 1].
+// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 1].
   fcmla v0.8h, v1.8h, v2.h[4], #0
-// STDERR-NO-FP16: :[[@LINE-1]]:{{[0-9]*}}: error: invalid operand for instruction
-// STDERR-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 3].
+// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 3].
   fcmla v0.4s, v1.4s, v2.s[2], #0
 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 1].
 

Modified: llvm/trunk/test/MC/AArch64/armv8.3a-rcpc.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.3a-rcpc.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.3a-rcpc.s (original)
+++ llvm/trunk/test/MC/AArch64/armv8.3a-rcpc.s Mon Dec 18 12:58:25 2017
@@ -18,9 +18,9 @@
 // CHECK: ldapr x0, [x0]     // encoding: [0x00,0xc0,0xbf,0xf8]
 // CHECK: ldapr w18, [x0]    // encoding: [0x12,0xc0,0xbf,0xb8]
 // CHECK: ldapr x15, [x0]    // encoding: [0x0f,0xc0,0xbf,0xf8]
-// CHECK-REQ: error: instruction requires: rcpc
-// CHECK-REQ: error: instruction requires: rcpc
-// CHECK-REQ: error: instruction requires: rcpc
-// CHECK-REQ: error: instruction requires: rcpc
+// CHECK-REQ: error: invalid operand for instruction
+// CHECK-REQ: error: invalid operand for instruction
+// CHECK-REQ: error: invalid operand for instruction
+// CHECK-REQ: error: invalid operand for instruction
 // CHECK-REQ: error: instruction requires: rcpc
 // CHECK-REQ: error: instruction requires: rcpc

Modified: llvm/trunk/test/MC/Mips/eva/invalid-noeva-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/eva/invalid-noeva-wrong-error.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/eva/invalid-noeva-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/eva/invalid-noeva-wrong-error.s Mon Dec 18 12:58:25 2017
@@ -19,51 +19,51 @@
 # RUN: FileCheck %s < %t1
 
         .set noat
-        cachee    31, 255($7)          # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
-        cachee    0, -256($4)          # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
-        cachee    5, -140($4)          # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
-        lbe       $10,-256($25)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lbe       $13,255($15)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lbe       $11,146($14)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lbue      $13,-256($v1)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lbue      $13,255($v0)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lbue      $13,-190($v1)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lhe       $13,-256($s5)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lhe       $12,255($s0)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lhe       $13,81($s0)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lhue      $s2,-256($v1)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lhue      $s2,255($v1)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lhue      $s6,-168($v0)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lle       $v0,-256($s5)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lle       $v1,255($s3)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lle       $v1,-71($s6)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwe       $15,255($a2)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwe       $13,-256($a2)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwe       $15,-200($a1)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwle      $s6,255($15)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwle      $s7,-256($10)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwle      $s7,-176($13)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwre      $zero,255($gp)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwre      $zero,-256($gp)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwre      $zero,-176($gp)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        prefe     14, -256($2)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        prefe     11, 255($3)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        prefe     14, -37($3)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        sbe       $s1,255($11)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        sbe       $s1,-256($10)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        sbe       $s3,0($14)           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        sce       $9,255($s2)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        sce       $12,-256($s5)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        sce       $13,-31($s7)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        she       $14,255($15)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        she       $14,-256($15)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        she       $9,235($11)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        swe       $ra,255($sp)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        swe       $ra,-256($sp)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        swe       $ra,-53($sp)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        swle      $9,255($s1)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        swle      $10,-256($s3)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        swle      $8,131($s5)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        swre      $s4,255($13)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        swre      $s4,-256($13)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        swre      $s2,86($14)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        cachee    31, 255($7)          # CHECK: :[[@LINE]]:23: error: expected memory with 9-bit signed offset
+        cachee    0, -256($4)          # CHECK: :[[@LINE]]:22: error: expected memory with 9-bit signed offset
+        cachee    5, -140($4)          # CHECK: :[[@LINE]]:22: error: expected memory with 9-bit signed offset
+        lbe       $10,-256($25)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lbe       $13,255($15)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lbe       $11,146($14)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lbue      $13,-256($v1)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lbue      $13,255($v0)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lbue      $13,-190($v1)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lhe       $13,-256($s5)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lhe       $12,255($s0)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lhe       $13,81($s0)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lhue      $s2,-256($v1)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lhue      $s2,255($v1)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lhue      $s6,-168($v0)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lle       $v0,-256($s5)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lle       $v1,255($s3)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lle       $v1,-71($s6)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lwe       $15,255($a2)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lwe       $13,-256($a2)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lwe       $15,-200($a1)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lwle      $s6,255($15)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lwle      $s7,-256($10)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lwle      $s7,-176($13)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lwre      $zero,255($gp)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lwre      $zero,-256($gp)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lwre      $zero,-176($gp)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        prefe     14, -256($2)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        prefe     11, 255($3)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        prefe     14, -37($3)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        sbe       $s1,255($11)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        sbe       $s1,-256($10)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        sbe       $s3,0($14)           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        sce       $9,255($s2)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        sce       $12,-256($s5)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        sce       $13,-31($s7)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        she       $14,255($15)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        she       $14,-256($15)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        she       $9,235($11)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        swe       $ra,255($sp)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        swe       $ra,-256($sp)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        swe       $ra,-53($sp)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        swle      $9,255($s1)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        swle      $10,-256($s3)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        swle      $8,131($s5)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        swre      $s4,255($13)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        swre      $s4,-256($13)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        swre      $s2,86($14)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset

Modified: llvm/trunk/test/MC/Mips/eva/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/eva/invalid.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/eva/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/eva/invalid.s Mon Dec 18 12:58:25 2017
@@ -5,31 +5,31 @@
 # RUN: FileCheck %s < %t1
 
     .set noat
-    cachee -1, 255($7) # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
-    cachee 32, 255($7) # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
-    prefe -1, 255($7)  # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
-    prefe 32, 255($7)  # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+    cachee -1, 255($7) # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
+    cachee 32, 255($7) # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
+    prefe -1, 255($7)  # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+    prefe 32, 255($7)  # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
     lle $33, 8($5)     # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-    lle $4, 8($33)     # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
-    lle $4, 512($5)    # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
-    lle $4, -513($5)   # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+    lle $4, 8($33)     # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
+    lle $4, 512($5)    # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
+    lle $4, -513($5)   # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
     lwe $33, 8($5)     # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-    lwe $4, 8($33)     # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
-    lwe $4, 512($5)    # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
-    lwe $4, -513($5)   # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+    lwe $4, 8($33)     # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
+    lwe $4, 512($5)    # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
+    lwe $4, -513($5)   # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
     sbe $33, 8($5)     # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-    sbe $4, 8($33)     # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
-    sbe $4, 512($5)    # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
-    sbe $4, -513($5)   # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+    sbe $4, 8($33)     # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
+    sbe $4, 512($5)    # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
+    sbe $4, -513($5)   # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
     sce $33, 8($5)     # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-    sce $4, 8($33)     # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
-    sce $4, 512($5)    # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
-    sce $4, -513($5)   # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+    sce $4, 8($33)     # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
+    sce $4, 512($5)    # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
+    sce $4, -513($5)   # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
     she $33, 8($5)     # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-    she $4, 8($33)     # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
-    she $4, 512($5)    # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
-    she $4, -513($5)   # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+    she $4, 8($33)     # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
+    she $4, 512($5)    # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
+    she $4, -513($5)   # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
     swe $33, 8($4)     # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-    swe $5, 8($34)     # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
-    swe $5, 512($4)    # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
-    swe $5, -513($4)   # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+    swe $5, 8($34)     # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
+    swe $5, 512($4)    # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
+    swe $5, -513($4)   # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset

Modified: llvm/trunk/test/MC/Mips/eva/invalid_R6.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/eva/invalid_R6.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/eva/invalid_R6.s (original)
+++ llvm/trunk/test/MC/Mips/eva/invalid_R6.s Mon Dec 18 12:58:25 2017
@@ -6,18 +6,18 @@
 # RUN: FileCheck %s < %t1
 
         .set noat
-        lwle      $s6,255($15)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwle      $s7,-256($10)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwle      $s7,-176($13)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwre      $zero,255($gp)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwre      $zero,-256($gp)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwre      $zero,-176($gp)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        swle      $9,255($s1)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        swle      $10,-256($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        swle      $8,131($s5)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        swre      $s4,255($13)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        swre      $s4,-256($13)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        swre      $s2,86($14)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwle      $s6,255($15)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lwle      $s7,-256($10)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lwle      $s7,-176($13)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lwre      $zero,255($gp)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lwre      $zero,-256($gp)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lwre      $zero,-176($gp)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        swle      $9,255($s1)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        swle      $10,-256($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        swle      $8,131($s5)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        swre      $s4,255($13)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        swre      $s4,-256($13)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        swre      $s2,86($14)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
         lle       $33, 8($5)         # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
         lle       $4, 8($33)         # CHECK: :[[@LINE]]:23: error: expected memory with 9-bit signed offset
         lle       $4, 512($5)        # CHECK: :[[@LINE]]:23: error: expected memory with 9-bit signed offset

Modified: llvm/trunk/test/MC/Mips/micromips-dsp/invalid-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-dsp/invalid-wrong-error.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-dsp/invalid-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/micromips-dsp/invalid-wrong-error.s Mon Dec 18 12:58:25 2017
@@ -4,4 +4,4 @@
 
   .set noat
   wrdsp $5, 128            # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  wrdsp $5, -1             # CHECK: :[[@LINE]]:13: error: expected 7-bit unsigned immediate
+  wrdsp $5, -1             # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate

Modified: llvm/trunk/test/MC/Mips/micromips/invalid-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips/invalid-wrong-error.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips/invalid-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/micromips/invalid-wrong-error.s Mon Dec 18 12:58:25 2017
@@ -6,8 +6,8 @@
   # the diagnostic for the 20-bit form. This isn't exactly wrong but it is
   # misleading. Ideally, we'd emit every way to achieve a valid match instead
   # of picking only one.
-  sdbbp -1            # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
+  sdbbp -1            # CHECK: :[[@LINE]]:9: error: expected 20-bit unsigned immediate
   sdbbp 1024          # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  syscall -1          # CHECK: :[[@LINE]]:11: error: expected 10-bit unsigned immediate
-  syscall $4          # CHECK: :[[@LINE]]:11: error: expected 10-bit unsigned immediate
+  syscall -1          # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
+  syscall $4          # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
   syscall 1024        # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled

Modified: llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s Mon Dec 18 12:58:25 2017
@@ -7,20 +7,38 @@
   # the diagnostic for the 10-bit form. This isn't exactly wrong but it is
   # misleading. Ideally, we'd emit every way to achieve a valid match instead
   # of picking only one.
+  teq $8, $9, $2           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
+  teq $8, $9, -1           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
   teq $8, $9, 16           # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  tge $8, $9, $2           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
+  tge $8, $9, -1           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
   tge $8, $9, 16           # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  tgeu $8, $9, $2          # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate
+  tgeu $8, $9, -1          # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate
   tgeu $8, $9, 16          # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  tlt $8, $9, $2           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
+  tlt $8, $9, -1           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
   tlt $8, $9, 16           # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  tltu $8, $9, $2          # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate
+  tltu $8, $9, -1          # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate
   tltu $8, $9, 16          # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  tne $8, $9, $2           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
+  tne $8, $9, -1           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
   tne $8, $9, 16           # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  syscall -1               # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
+  syscall $4               # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
   syscall 1024             # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
   ldc2 $1, -2049($12)      # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
   ldc2 $1, 2048($12)       # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  ldc2 $1, 1023($32)       # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
   lwc2 $1, -2049($4)       # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
   lwc2 $1, 2048($4)        # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  lwc2 $1, 16($32)         # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
   sdc2 $1, -2049($16)      # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
   sdc2 $1, 2048($16)       # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  sdc2 $1, 8($32)          # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
   swc2 $1, -2049($17)      # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
   swc2 $1, 2048($17)       # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  swc2 $1, 777($32)        # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
   lwc2 $11, -1025($12)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
   lwc2 $11, 1024($12)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

Modified: llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/invalid.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/invalid.s Mon Dec 18 12:58:25 2017
@@ -351,21 +351,3 @@
   bnezc $2, -4194303       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
   bnezc $2, 4194304        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
   bnezc $2, 4194303        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  teq $8, $9, $2           # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate
-  teq $8, $9, -1           # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate
-  tge $8, $9, $2           # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate
-  tge $8, $9, -1           # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate
-  tgeu $8, $9, $2          # CHECK: :[[@LINE]]:16: error: expected 4-bit unsigned immediate
-  tgeu $8, $9, -1          # CHECK: :[[@LINE]]:16: error: expected 4-bit unsigned immediate
-  tlt $8, $9, $2           # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate
-  tlt $8, $9, -1           # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate
-  tltu $8, $9, $2          # CHECK: :[[@LINE]]:16: error: expected 4-bit unsigned immediate
-  tltu $8, $9, -1          # CHECK: :[[@LINE]]:16: error: expected 4-bit unsigned immediate
-  tne $8, $9, $2           # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate
-  tne $8, $9, -1           # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate
-  syscall -1               # CHECK: :[[@LINE]]:11: error: expected 10-bit unsigned immediate
-  syscall $4               # CHECK: :[[@LINE]]:11: error: expected 10-bit unsigned immediate
-  ldc2 $1, 1023($32)       # CHECK: :[[@LINE]]:12: error: expected memory with 11-bit signed offset
-  lwc2 $1, 16($32)         # CHECK: :[[@LINE]]:12: error: expected memory with 11-bit signed offset
-  sdc2 $1, 8($32)          # CHECK: :[[@LINE]]:12: error: expected memory with 11-bit signed offset
-  swc2 $1, 777($32)        # CHECK: :[[@LINE]]:12: error: expected memory with 11-bit signed offset

Modified: llvm/trunk/test/MC/Mips/mips1/invalid-mips2-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/invalid-mips2-wrong-error.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/invalid-mips2-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/mips1/invalid-mips2-wrong-error.s Mon Dec 18 12:58:25 2017
@@ -6,11 +6,11 @@
 # RUN: FileCheck %s < %t1
 
 	.set noat
-        ldc2      $8,-21181($at)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        ldc2      $8,-1024($at)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        ldc2      $8,-21181($at)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
+        ldc2      $8,-1024($at)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
         ldc3      $29,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        ll        $v0,-7321($s2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        sc        $t7,18904($s3)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        sdc2      $20,23157($s2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        sdc2      $20,-1024($s2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        ll        $v0,-7321($s2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        sc        $t7,18904($s3)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        sdc2      $20,23157($s2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
+        sdc2      $20,-1024($s2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
         sdc3      $12,5835($t2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

Modified: llvm/trunk/test/MC/Mips/mips1/invalid-mips3-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/invalid-mips3-wrong-error.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/invalid-mips3-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/mips1/invalid-mips3-wrong-error.s Mon Dec 18 12:58:25 2017
@@ -6,14 +6,14 @@
 # RUN: FileCheck %s < %t1
 
 	.set noat
-        ldc2      $8,-21181($at)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        ldc2      $20,-1024($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        ldc2      $8,-21181($at)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
+        ldc2      $20,-1024($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
         ldl       $24,-4167($24)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         ldr       $14,-30358($s4)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        ll        $v0,-7321($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        sc        $15,18904($s3)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        scd       $15,-8243($sp)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        sdc2      $20,23157($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        sdc2      $20,-1024($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        ll        $v0,-7321($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        sc        $15,18904($s3)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        scd       $15,-8243($sp)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        sdc2      $20,23157($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
+        sdc2      $20,-1024($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
         sdl       $a3,-20961($s8)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         sdr       $11,-20423($12)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

Modified: llvm/trunk/test/MC/Mips/mips1/invalid-mips3.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/invalid-mips3.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/invalid-mips3.s (original)
+++ llvm/trunk/test/MC/Mips/mips1/invalid-mips3.s Mon Dec 18 12:58:25 2017
@@ -54,8 +54,8 @@
         floor.l.s $f12,$f5          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         floor.w.d $f14,$f11         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         floor.w.s $f8,$f9           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        lld       $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwu       $s3,-24086($v1)   # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+        lld       $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
+        lwu       $s3,-24086($v1)   # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset
         round.l.d $f12,$f1          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         round.l.s $f25,$f5          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         round.w.d $f6,$f4           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

Modified: llvm/trunk/test/MC/Mips/mips1/invalid-mips4-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/invalid-mips4-wrong-error.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/invalid-mips4-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/mips1/invalid-mips4-wrong-error.s Mon Dec 18 12:58:25 2017
@@ -8,14 +8,14 @@
 	.set noat
         bc1fl     $fcc7,27          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         bc1tl     $fcc7,27          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        ldc2      $8,-21181($at)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        ldc2      $20,-1024($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        ldc2      $8,-21181($at)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
+        ldc2      $20,-1024($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
         ldl       $24,-4167($24)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         ldr       $14,-30358($s4)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        ll        $v0,-7321($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        sc        $15,18904($s3)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        scd       $15,-8243($sp)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        sdc2      $20,23157($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        sdc2      $20,-1024($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        ll        $v0,-7321($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        sc        $15,18904($s3)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        scd       $15,-8243($sp)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        sdc2      $20,23157($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
+        sdc2      $20,-1024($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
         sdl       $a3,-20961($s8)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         sdr       $11,-20423($12)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

Modified: llvm/trunk/test/MC/Mips/mips1/invalid-mips4.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/invalid-mips4.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/invalid-mips4.s (original)
+++ llvm/trunk/test/MC/Mips/mips1/invalid-mips4.s Mon Dec 18 12:58:25 2017
@@ -69,8 +69,8 @@
         movz      $a1,$s6,$9        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         movz.d    $f12,$f29,$9      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         movz.s    $f25,$f7,$v1      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        lld       $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwu       $s3,-24086($v1)   # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+        lld       $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
+        lwu       $s3,-24086($v1)   # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset
         round.l.d $f12,$f1          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         round.l.s $f25,$f5          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         round.w.d $f6,$f4           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

Modified: llvm/trunk/test/MC/Mips/mips1/invalid-mips5.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/invalid-mips5.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/invalid-mips5.s (original)
+++ llvm/trunk/test/MC/Mips/mips1/invalid-mips5.s Mon Dec 18 12:58:25 2017
@@ -88,5 +88,5 @@
         sdxc1     $f11,$a2($t2)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         suxc1     $f12,$k1($t1)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         swxc1     $f19,$t0($k0)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        ldc1      $f11,16391($s0)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        sdc1      $f31,30574($t5)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        ldc1      $f11,16391($s0)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
+        sdc1      $f31,30574($t5)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset

Modified: llvm/trunk/test/MC/Mips/mips2/invalid-mips3-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips2/invalid-mips3-wrong-error.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips2/invalid-mips3-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/mips2/invalid-mips3-wrong-error.s Mon Dec 18 12:58:25 2017
@@ -9,6 +9,6 @@
         dmult     $s7,$a5           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         ldl       $t8,-4167($t8)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         ldr       $t2,-30358($s4)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        scd       $t3,-8243($sp)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        scd       $t3,-8243($sp)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
         sdl       $a3,-20961($s8)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         sdr       $a7,-20423($t0)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

Modified: llvm/trunk/test/MC/Mips/mips2/invalid-mips3.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips2/invalid-mips3.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips2/invalid-mips3.s (original)
+++ llvm/trunk/test/MC/Mips/mips2/invalid-mips3.s Mon Dec 18 12:58:25 2017
@@ -50,8 +50,8 @@
         eret                         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         floor.l.d  $f26,$f7          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         floor.l.s  $f12,$f5          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        lld        $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwu        $s3,-24086($v1)   # CHECK: :[[@LINE]]:24: error: invalid operand for instruction
+        lld        $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
+        lwu        $s3,-24086($v1)   # CHECK: :[[@LINE]]:24: error: expected memory with 12-bit signed offset
         round.l.d  $f12,$f1          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         round.l.s  $f25,$f5          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         trunc.l.d   $f23,$f23        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

Modified: llvm/trunk/test/MC/Mips/mips2/invalid-mips4-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips2/invalid-mips4-wrong-error.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips2/invalid-mips4-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/mips2/invalid-mips4-wrong-error.s Mon Dec 18 12:58:25 2017
@@ -8,6 +8,6 @@
 	.set noat
         bc1fl     $fcc7,27        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
         bc1tl     $fcc7,27        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
-        scd       $15,-8243($sp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        scd       $15,-8243($sp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
         sdl       $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         sdr       $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

Modified: llvm/trunk/test/MC/Mips/mips2/invalid-mips4.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips2/invalid-mips4.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips2/invalid-mips4.s (original)
+++ llvm/trunk/test/MC/Mips/mips2/invalid-mips4.s Mon Dec 18 12:58:25 2017
@@ -48,7 +48,7 @@
         floor.l.s $f12,$f5        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         ldxc1     $f8,$s7($15)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         lwxc1     $f12,$s1($s8)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        lwu       $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+        lwu       $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset
         movf      $gp,$8,$fcc0    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         movf      $gp,$8,$fcc7    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         movf.d    $f6,$f11,$fcc0  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

Modified: llvm/trunk/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s Mon Dec 18 12:58:25 2017
@@ -11,8 +11,8 @@
         lwr       $zero,-19147($gp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         swl       $15,13694($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         swr       $s1,-26590($14)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwle      $s4,-4231($15)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwre      $zero,-19147($gp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        swle      $15,13694($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        swre      $24, 5($3)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        swre      $s1,-26590($14)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwle      $s4,-4231($15)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lwre      $zero,-19147($gp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        swle      $15,13694($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        swre      $24, 5($3)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        swre      $s1,-26590($14)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset

Modified: llvm/trunk/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s Mon Dec 18 12:58:25 2017
@@ -11,13 +11,13 @@
         bc1any4t  $fcc2,4             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         ldc2 $1, -2049($12)           # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
         ldc2 $1, 2048($12)            # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
-        ldc2 $1, 1023($32)            # CHECK: :[[@LINE]]:18: error: expected memory with 11-bit signed offset
+        ldc2 $1, 1023($32)            # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
         lwc2 $1, -2049($4)            # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
         lwc2 $1, 2048($4)             # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
-        lwc2 $1, 16($32)              # CHECK: :[[@LINE]]:18: error: expected memory with 11-bit signed offset
+        lwc2 $1, 16($32)              # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
         sdc2 $1, -2049($16)           # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
         sdc2 $1, 2048($16)            # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
-        sdc2 $1, 8($32)               # CHECK: :[[@LINE]]:18: error: expected memory with 11-bit signed offset
+        sdc2 $1, 8($32)               # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
         swc2 $1, -2049($17)           # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
         swc2 $1, 2048($17)            # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
-        swc2 $1, 777($32)             # CHECK: :[[@LINE]]:18: error: expected memory with 11-bit signed offset
+        swc2 $1, 777($32)             # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset

Modified: llvm/trunk/test/MC/Mips/mips32r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/invalid.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/invalid.s Mon Dec 18 12:58:25 2017
@@ -27,17 +27,17 @@ local_label:
         lhu $35, 8($2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         lhue $36, 8($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         lh  $2, 8($34)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        lhe $4, 8($33)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lhe $4, 8($33)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
         lhu $4, 8($35)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        lhue $4, 8($37)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lhue $4, 8($37)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
         lh  $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
         lh  $2, 65536($4)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        lhe $4, -512($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lhe $4, 512($2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lhe $4, -512($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lhe $4, 512($2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
         lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
         lhu $4, 65536($2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        lhue $4, -512($2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lhue $4, 512($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lhue $4, -512($2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lhue $4, 512($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
         // FIXME: Following tests are temporarily disabled, until "PredicateControl not in hierarchy" problem is resolved
         bltl  $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         bltul $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

Modified: llvm/trunk/test/MC/Mips/mips64/invalid-mips64r2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64/invalid-mips64r2.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64/invalid-mips64r2.s (original)
+++ llvm/trunk/test/MC/Mips/mips64/invalid-mips64r2.s Mon Dec 18 12:58:25 2017
@@ -29,13 +29,13 @@
         seb       $25,$15             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         seh       $v1,$12             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         wsbh      $k1,$9              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        dins $2, $3, -1, 1            # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
-        dins $2, $3, 64, 1            # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
-        dinsm $2, $3, -1, 1           # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
-        dinsm $2, $3, 32, 1           # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
-        dinsm $2, $3, 31, 0           # CHECK: :[[@LINE]]:27: error: invalid operand for instruction
-        dinsm $2, $3, 31, 65          # CHECK: :[[@LINE]]:27: error: invalid operand for instruction
-        dinsu $2, $3, 31, 1           # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
-        dinsu $2, $3, 64, 1           # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
-        dinsu $2, $3, 63, 0           # CHECK: :[[@LINE]]:27: error: invalid operand for instruction
-        dinsu $2, $3, 32, 33          # CHECK: :[[@LINE]]:27: error: invalid operand for instruction
+        dins $2, $3, -1, 1            # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
+        dins $2, $3, 64, 1            # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
+        dinsm $2, $3, -1, 1           # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
+        dinsm $2, $3, 32, 1           # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
+        dinsm $2, $3, 31, 0           # CHECK: :[[@LINE]]:27: error: expected immediate in range 2 .. 64
+        dinsm $2, $3, 31, 65          # CHECK: :[[@LINE]]:27: error: expected immediate in range 2 .. 64
+        dinsu $2, $3, 31, 1           # CHECK: :[[@LINE]]:23: error: expected immediate in range 32 .. 63
+        dinsu $2, $3, 64, 1           # CHECK: :[[@LINE]]:23: error: expected immediate in range 32 .. 63
+        dinsu $2, $3, 63, 0           # CHECK: :[[@LINE]]:27: error: expected immediate in range 1 .. 32
+        dinsu $2, $3, 32, 33          # CHECK: :[[@LINE]]:27: error: expected immediate in range 1 .. 32

Modified: llvm/trunk/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s Mon Dec 18 12:58:25 2017
@@ -11,7 +11,7 @@
         lwr       $zero,-19147($gp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         swl       $15,13694($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         swr       $s1,-26590($14)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwle      $s4,-4231($15)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwre      $zero,-19147($gp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        swle      $15,13694($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        swre      $s1,-26590($14)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwle      $s4,-4231($15)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lwre      $zero,-19147($gp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        swle      $15,13694($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        swre      $s1,-26590($14)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset

Modified: llvm/trunk/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s Mon Dec 18 12:58:25 2017
@@ -17,7 +17,7 @@
         lwr       $zero,-19147($gp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         swl       $15,13694($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         swr       $s1,-26590($14)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwle      $s4,-4231($15)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwre      $zero,-19147($gp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        swle      $15,13694($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        swre      $s1,-26590($14)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwle      $s4,-4231($15)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lwre      $zero,-19147($gp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        swle      $15,13694($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        swre      $s1,-26590($14)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset

Modified: llvm/trunk/test/MC/Mips/mips64r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/invalid.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/invalid.s Mon Dec 18 12:58:25 2017
@@ -57,17 +57,17 @@ local_label:
         lhu $35, 8($2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         lhue $36, 8($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         lh  $2, 8($34)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        lhe $4, 8($33)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lhe $4, 8($33)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
         lhu $4, 8($35)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        lhue $4, 8($37)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lhue $4, 8($37)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
         lh  $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
         lh  $2, 65536($4)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        lhe $4, -512($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lhe $4, 512($2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lhe $4, -512($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lhe $4, 512($2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
         lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
         lhu $4, 65536($2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        lhue $4, -512($2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lhue $4, 512($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lhue $4, -512($2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lhue $4, 512($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
         // FIXME: Following tests are temporarily disabled, until "PredicateControl not in hierarchy" problem is resolved
         bltl  $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         bltul $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

Modified: llvm/trunk/test/MC/Mips/msa/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/msa/invalid.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/msa/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/msa/invalid.s Mon Dec 18 12:58:25 2017
@@ -107,22 +107,22 @@
     copy_s.h $2, $w9[8]      # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate
     copy_s.w $2, $w9[-1]     # CHECK: :[[@LINE]]:22: error: expected 2-bit unsigned immediate
     copy_s.w $2, $w9[4]      # CHECK: :[[@LINE]]:22: error: expected 2-bit unsigned immediate
-    copy_s.d $2, $w9[-1]     # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
-    copy_s.d $2, $w9[2]      # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
+    copy_s.d $2, $w9[-1]     # CHECK: :[[@LINE]]:22: error: expected 1-bit unsigned immediate
+    copy_s.d $2, $w9[2]      # CHECK: :[[@LINE]]:22: error: expected 1-bit unsigned immediate
     copy_u.b $2, $w9[-1]     # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate
     copy_u.b $2, $w9[16]     # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate
     copy_u.h $2, $w9[-1]     # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate
     copy_u.h $2, $w9[8]      # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate
-    copy_u.w $2, $w9[-1]     # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
-    copy_u.w $2, $w9[4]      # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
+    copy_u.w $2, $w9[-1]     # CHECK: :[[@LINE]]:22: error: expected 2-bit unsigned immediate
+    copy_u.w $2, $w9[4]      # CHECK: :[[@LINE]]:22: error: expected 2-bit unsigned immediate
     insert.b $w9[-1], $2     # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate
     insert.b $w9[16], $2     # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate
     insert.h $w9[-1], $2     # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
     insert.h $w9[8], $2      # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
     insert.w $w9[-1], $2     # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate
     insert.w $w9[4], $2      # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate
-    insert.d $w9[-1], $2     # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
-    insert.d $w9[2], $2      # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
+    insert.d $w9[-1], $2     # CHECK: :[[@LINE]]:18: error: expected 1-bit unsigned immediate
+    insert.d $w9[2], $2      # CHECK: :[[@LINE]]:18: error: expected 1-bit unsigned immediate
     insve.b $w25[-1], $w9[0] # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate
     insve.b $w25[16], $w9[0] # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate
     insve.h $w24[-1], $w2[0] # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate

Modified: llvm/trunk/test/MC/Mips/target-soft-float.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/target-soft-float.s?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/target-soft-float.s (original)
+++ llvm/trunk/test/MC/Mips/target-soft-float.s Mon Dec 18 12:58:25 2017
@@ -269,10 +269,10 @@ foo:
   # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
   ldc1       $f2, 16($7)
   # FIXME: LDC1 is correctly rejected but the wrong error message is emitted.
-  # 32: :[[@LINE-2]]:19: error: invalid operand for instruction
+  # 32: :[[@LINE-2]]:19: error: expected memory with 16-bit signed offset
   lwc1       $f2, 16($7)
   # FIXME: LWC1 is correctly rejected but the wrong error message is emitted.
-  # 32: :[[@LINE-2]]:19: error: invalid operand for instruction
+  # 32: :[[@LINE-2]]:19: error: expected memory with 16-bit signed offset
   madd.s     $f2, $f2, $f2, $f2
   # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
   mfc1       $7, $f2
@@ -313,7 +313,7 @@ foo:
   # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
   sdc1       $f2, 16($7)
   # FIXME: SDC1 is correctly rejected but the wrong error message is emitted.
-  # 32: :[[@LINE-2]]:19: error: invalid operand for instruction
+  # 32: :[[@LINE-2]]:19: error: expected memory with 16-bit signed offset
   sqrt.d     $f2, $f2
   # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
   sqrt.s     $f2, $f2
@@ -324,7 +324,7 @@ foo:
   # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
   swc1       $f2, 16($7)
   # FIXME: SWC1 is correctly rejected but the wrong error message is emitted.
-  # 32: :[[@LINE-2]]:19: error: invalid operand for instruction
+  # 32: :[[@LINE-2]]:19: error: expected memory with 16-bit signed offset
   trunc.w.d  $f2, $f2
   # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
   trunc.w.s  $f2, $f2

Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=321024&r1=321023&r2=321024&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Dec 18 12:58:25 2017
@@ -2764,8 +2764,7 @@ static void emitCustomOperandParsing(raw
   // a better error handling.
   OS << "OperandMatchResultTy " << Target.getName() << ClassName << "::\n"
      << "MatchOperandParserImpl(OperandVector"
-     << " &Operands,\n                       StringRef Mnemonic,\n"
-     << "                       bool ParseForAllFeatures) {\n";
+     << " &Operands,\n                       StringRef Mnemonic) {\n";
 
   // Emit code to get the available features.
   OS << "  // Get the current feature set.\n";
@@ -2803,9 +2802,10 @@ static void emitCustomOperandParsing(raw
 
   // Emit check that the required features are available.
   OS << "    // check if the available features match\n";
-  OS << "    if (!ParseForAllFeatures && (AvailableFeatures & "
-        "it->RequiredFeatures) != it->RequiredFeatures)\n";
-  OS << "        continue;\n\n";
+  OS << "    if ((AvailableFeatures & it->RequiredFeatures) "
+     << "!= it->RequiredFeatures) {\n";
+  OS << "      continue;\n";
+  OS << "    }\n\n";
 
   // Emit check to ensure the operand number matches.
   OS << "    // check if the operand in question has a custom parser.\n";
@@ -2993,8 +2993,7 @@ void AsmMatcherEmitter::run(raw_ostream
   if (!Info.OperandMatchInfo.empty()) {
     OS << "  OperandMatchResultTy MatchOperandParserImpl(\n";
     OS << "    OperandVector &Operands,\n";
-    OS << "    StringRef Mnemonic,\n";
-    OS << "    bool ParseForAllFeatures = false);\n";
+    OS << "    StringRef Mnemonic);\n";
 
     OS << "  OperandMatchResultTy tryCustomParseOperand(\n";
     OS << "    OperandVector &Operands,\n";
@@ -3270,9 +3269,7 @@ void AsmMatcherEmitter::run(raw_ostream
   OS << "  for (const MatchEntry *it = MnemonicRange.first, "
      << "*ie = MnemonicRange.second;\n";
   OS << "       it != ie; ++it) {\n";
-  OS << "    bool HasRequiredFeatures =\n";
-  OS << "      (AvailableFeatures & it->RequiredFeatures) == "
-        "it->RequiredFeatures;\n";
+
   OS << "    DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Trying to match opcode \"\n";
   OS << "                                          << MII.getName(it->Opcode) << \"\\n\");\n";
 
@@ -3363,8 +3360,7 @@ void AsmMatcherEmitter::run(raw_ostream
   OS << "        }\n";
   OS << "        // If the target matcher returned a specific error code use\n";
   OS << "        // that, else use the one from the generic matcher.\n";
-  OS << "        if (TargetDiag != Match_InvalidOperand && "
-        "HasRequiredFeatures)\n";
+  OS << "        if (TargetDiag != Match_InvalidOperand)\n";
   OS << "          Diag = TargetDiag;\n";
   OS << "      }\n";
   OS << "      // If current formal operand wasn't matched and it is optional\n"
@@ -3406,8 +3402,7 @@ void AsmMatcherEmitter::run(raw_ostream
     OS << "      // target predicate, that diagnostic is preferred.\n";
     OS << "      if (!HadMatchOtherThanPredicate &&\n";
     OS << "          (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {\n";
-    OS << "        if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag "
-          "!= Match_InvalidOperand))\n";
+    OS << "        if (Diag != Match_InvalidOperand || ErrorInfo != ActualIdx)\n";
     OS << "          RetCode = Diag;\n";
     OS << "        ErrorInfo = ActualIdx;\n";
     OS << "      }\n";
@@ -3428,7 +3423,8 @@ void AsmMatcherEmitter::run(raw_ostream
   OS << "    }\n";
 
   // Emit check that the required features are available.
-  OS << "    if (!HasRequiredFeatures) {\n";
+  OS << "    if ((AvailableFeatures & it->RequiredFeatures) "
+     << "!= it->RequiredFeatures) {\n";
   if (!ReportMultipleNearMisses)
     OS << "      HadMatchOtherThanFeatures = true;\n";
   OS << "      uint64_t NewMissingFeatures = it->RequiredFeatures & "




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