[llvm] r321013 - [PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation.

[Benjamin Kramer via llvm-commits]

Author: d0k
Date: Mon Dec 18 11:21:56 2017
New Revision: 321013

URL: http://llvm.org/viewvc/llvm-project?rev=321013&view=rev
Log:
[PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation.

This has the same issue as the early pass disabled in r321010.

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
    llvm/trunk/test/CodeGen/PowerPC/fast-isel-call.ll
    llvm/trunk/test/CodeGen/PowerPC/setcc-logic.ll
    llvm/trunk/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll

Modified: llvm/trunk/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCPreEmitPeephole.cpp?rev=321013&r1=321012&r2=321013&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCPreEmitPeephole.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCPreEmitPeephole.cpp Mon Dec 18 11:21:56 2017
@@ -35,7 +35,7 @@ STATISTIC(NumRemovedInPreEmit,
           "Number of instructions deleted in pre-emit peephole");
 
 static cl::opt<bool>
-RunPreEmitPeephole("ppc-late-peephole", cl::Hidden, cl::init(true),
+RunPreEmitPeephole("ppc-late-peephole", cl::Hidden, cl::init(false),
                    cl::desc("Run pre-emit peephole optimizations."));
 
 namespace {

Modified: llvm/trunk/test/CodeGen/PowerPC/fast-isel-call.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/fast-isel-call.ll?rev=321013&r1=321012&r2=321013&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/fast-isel-call.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/fast-isel-call.ll Mon Dec 18 11:21:56 2017
@@ -2,7 +2,7 @@
 ; registers and with -fast-isel-abort=1 turned on the test case will then fail.
 ; When fastisel better supports VSX fix up this test case.
 ;
-; RUN: llc < %s -O0 -verify-machineinstrs -mattr=-vsx -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -mattr=-vsx -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-late-peephole=true | FileCheck %s --check-prefix=ELF64
 
 define i32 @t1(i8 signext %a) nounwind {
   %1 = sext i8 %a to i32

Modified: llvm/trunk/test/CodeGen/PowerPC/setcc-logic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/setcc-logic.ll?rev=321013&r1=321012&r2=321013&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/setcc-logic.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/setcc-logic.ll Mon Dec 18 11:21:56 2017
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -ppc-gpr-icmps=all -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown | FileCheck %s
+; RUN: llc < %s -ppc-gpr-icmps=all -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -ppc-convert-rr-to-ri=true | FileCheck %s
 
 define zeroext i1 @all_bits_clear(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: all_bits_clear:

Modified: llvm/trunk/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll?rev=321013&r1=321012&r2=321013&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll Mon Dec 18 11:21:56 2017
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -ppc-late-peephole=true < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
 ; RUN:  --check-prefix=CHECK-BE
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \