[PATCH] D41350: [DAGCombine] Improve ReduceLoadWidth for SRL

[Sam Parker via Phabricator via llvm-commits]

samparker updated this revision to Diff 127380.
samparker added a comment.

Added some tests to handle non-byte shifts and masks, which highlighted that those cases weren't handled! This fix means that I've reverted one of the x86 test changes too.


https://reviews.llvm.org/D41350

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/ARM/shift-combine.ll
  test/CodeGen/X86/h-registers-1.ll

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