[llvm] r320844 - [X86] Remove the 'Requires' In64BitMode/Not64BitMode from the LWP instructions.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Fri Dec 15 11:01:49 2017
New Revision: 320844

URL: http://llvm.org/viewvc/llvm-project?rev=320844&view=rev
Log:
[X86] Remove the 'Requires' In64BitMode/Not64BitMode from the LWP instructions.

These aren't doing anything due to a top level "let Predicates =". I think the GR32/GR64 register class protects these anyway.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=320844&r1=320843&r2=320844&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Fri Dec 15 11:01:49 2017
@@ -2571,17 +2571,17 @@ let Predicates = [HasLWP], SchedRW = [Wr
 
 def LLWPCB : I<0x12, MRM0r, (outs), (ins GR32:$src), "llwpcb\t$src",
                [(int_x86_llwpcb GR32:$src)], IIC_LWP>,
-               XOP, XOP9, Requires<[Not64BitMode]>;
+               XOP, XOP9;
 def SLWPCB : I<0x12, MRM1r, (outs GR32:$dst), (ins), "slwpcb\t$dst",
                [(set GR32:$dst, (int_x86_slwpcb))], IIC_LWP>,
-               XOP, XOP9, Requires<[Not64BitMode]>;
+               XOP, XOP9;
 
 def LLWPCB64 : I<0x12, MRM0r, (outs), (ins GR64:$src), "llwpcb\t$src",
                  [(int_x86_llwpcb GR64:$src)], IIC_LWP>,
-                 XOP, XOP9, VEX_W, Requires<[In64BitMode]>;
+                 XOP, XOP9, VEX_W;
 def SLWPCB64 : I<0x12, MRM1r, (outs GR64:$dst), (ins), "slwpcb\t$dst",
                  [(set GR64:$dst, (int_x86_slwpcb))], IIC_LWP>,
-                 XOP, XOP9, VEX_W, Requires<[In64BitMode]>;
+                 XOP, XOP9, VEX_W;
 
 multiclass lwpins_intr<RegisterClass RC> {
   def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl),