[PATCH] D41225: [RISCV] enable emission of alias instructions by default

[Alex Bradbury via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL320797: [RISCV] Enable emission of alias instructions by default (authored by asb, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D41225?vs=126905&id=127081#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D41225

Files:
  llvm/trunk/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
  llvm/trunk/test/CodeGen/RISCV/addc-adde-sube-subc.ll
  llvm/trunk/test/CodeGen/RISCV/alloca.ll
  llvm/trunk/test/CodeGen/RISCV/alu32.ll
  llvm/trunk/test/CodeGen/RISCV/bare-select.ll
  llvm/trunk/test/CodeGen/RISCV/blockaddress.ll
  llvm/trunk/test/CodeGen/RISCV/branch.ll
  llvm/trunk/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
  llvm/trunk/test/CodeGen/RISCV/byval.ll
  llvm/trunk/test/CodeGen/RISCV/calling-conv-sext-zext.ll
  llvm/trunk/test/CodeGen/RISCV/calling-conv.ll
  llvm/trunk/test/CodeGen/RISCV/calls.ll
  llvm/trunk/test/CodeGen/RISCV/div.ll
  llvm/trunk/test/CodeGen/RISCV/fp128.ll
  llvm/trunk/test/CodeGen/RISCV/frame.ll
  llvm/trunk/test/CodeGen/RISCV/i32-icmp.ll
  llvm/trunk/test/CodeGen/RISCV/imm.ll
  llvm/trunk/test/CodeGen/RISCV/indirectbr.ll
  llvm/trunk/test/CodeGen/RISCV/jumptable.ll
  llvm/trunk/test/CodeGen/RISCV/mem.ll
  llvm/trunk/test/CodeGen/RISCV/mul.ll
  llvm/trunk/test/CodeGen/RISCV/rem.ll
  llvm/trunk/test/CodeGen/RISCV/rotl-rotr.ll
  llvm/trunk/test/CodeGen/RISCV/select-cc.ll
  llvm/trunk/test/CodeGen/RISCV/sext-zext-trunc.ll
  llvm/trunk/test/CodeGen/RISCV/shifts.ll
  llvm/trunk/test/CodeGen/RISCV/wide-mem.ll
  llvm/trunk/test/MC/RISCV/fixups.s
  llvm/trunk/test/MC/RISCV/priv-valid.s
  llvm/trunk/test/MC/RISCV/relocations.s
  llvm/trunk/test/MC/RISCV/rv32a-valid.s
  llvm/trunk/test/MC/RISCV/rv32c-only-valid.s
  llvm/trunk/test/MC/RISCV/rv32c-valid.s
  llvm/trunk/test/MC/RISCV/rv32d-valid.s
  llvm/trunk/test/MC/RISCV/rv32dc-valid.s
  llvm/trunk/test/MC/RISCV/rv32f-valid.s
  llvm/trunk/test/MC/RISCV/rv32fc-valid.s
  llvm/trunk/test/MC/RISCV/rv32i-aliases-invalid.s
  llvm/trunk/test/MC/RISCV/rv32i-aliases-valid.s
  llvm/trunk/test/MC/RISCV/rv32i-valid.s
  llvm/trunk/test/MC/RISCV/rv32m-valid.s
  llvm/trunk/test/MC/RISCV/rv64a-valid.s
  llvm/trunk/test/MC/RISCV/rv64c-valid.s
  llvm/trunk/test/MC/RISCV/rv64d-aliases-valid.s
  llvm/trunk/test/MC/RISCV/rv64d-valid.s
  llvm/trunk/test/MC/RISCV/rv64f-aliases-valid.s
  llvm/trunk/test/MC/RISCV/rv64f-valid.s
  llvm/trunk/test/MC/RISCV/rv64i-aliases-invalid.s
  llvm/trunk/test/MC/RISCV/rv64i-aliases-valid.s
  llvm/trunk/test/MC/RISCV/rv64i-valid.s
  llvm/trunk/test/MC/RISCV/rv64m-valid.s
  llvm/trunk/test/MC/RISCV/rvd-aliases-valid.s
  llvm/trunk/test/MC/RISCV/rvf-aliases-valid.s
  llvm/trunk/test/MC/RISCV/rvi-aliases-valid.s

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