[PATCH] D41216: [RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero

[Shiva Chen via Phabricator via llvm-commits]

shiva0217 created this revision.
shiva0217 added a reviewer: asb.
Herald added subscribers: sabuasal, jordy.potman.lists, johnrusso, rbar.

c.slli/c.srli/c.srai shift amount constraint should accrding to rv32/rv64.
For rv32, shift amount constraint should be [1, 31].
For rv64, shift amount constraint should be [1, 63].

Add uimmlog2xlennonzero to reflect the constraints.


Repository:
  rL LLVM

https://reviews.llvm.org/D41216

Files:
  lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  lib/Target/RISCV/RISCVInstrInfoC.td
  test/MC/RISCV/rv32c-invalid.s
  test/MC/RISCV/rv64c-invalid.s
  test/MC/RISCV/rv64c-valid.s

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