[PATCH] D41126: [SelectionDAG] Fixed f16-from-vector promotion problem

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Are you running with asserts disabled? I see:
ScalarizeVectorOperand Op #0: t34: f32 = fp16_to_fp t25

LLVM ERROR: Do not know how to scalarize this operator's operand!

and sure enough ScalarizeVectorOperand doesn't handle this.



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Comment at: test/CodeGen/AMDGPU/unpack-half.ll:20
+  %7 = extractelement <2 x i32> %bc, i32 1
+  call void @llvm.amdgcn.tbuffer.store.i32(i32 %7, <4 x i32> undef, i32 0, i32 4, i32 %0, i32 0, i32 4, i32 4, i1 true, i1 true) #0
+  ret void
----------------
tpr wrote:
> arsenm wrote:
> > You can probably replace the intrinsics with a regular load and store
> That made it crash, probably because I didn't get the right address space or something. I think it's easier to leave it with the intrinsics from the original reproducer.
Replacing this with   
%tmp =  load volatile float, float addrspace(1)* undef
and
store volatile i32 %tmp6, i32 addrspace(1)* undef

works for me



https://reviews.llvm.org/D41126