[llvm] r320569 - [RISCV] Implement floating point assembler pseudo instructions
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 13 03:37:19 PST 2017
Author: asb
Date: Wed Dec 13 03:37:19 2017
New Revision: 320569
URL: http://llvm.org/viewvc/llvm-project?rev=320569&view=rev
Log:
[RISCV] Implement floating point assembler pseudo instructions
Adds the assembler aliases for the floating point instructions
which can be mapped to a single canonical instruction. The missing
pseudo instructions (flw, fld, fsw, fsd) are marked as TODO. Other
things, like for example PCREL_LO, have to be implemented first.
This patch builds upon D40902.
Differential Revision: https://reviews.llvm.org/D41071
Patch by Mario Werner.
Added:
llvm/trunk/test/MC/RISCV/rvd-aliases-valid.s
llvm/trunk/test/MC/RISCV/rvf-aliases-valid.s
Modified:
llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td
llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td?rev=320569&r1=320568&r2=320569&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td Wed Dec 13 03:37:19 2017
@@ -159,3 +159,16 @@ def FMV_D_X : FPUnaryOp_r<0b1111001, 0b0
let rs2 = 0b00000;
}
} // Predicates = [HasStdExtD, IsRV64]
+
+//===----------------------------------------------------------------------===//
+// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtD] in {
+// TODO fld
+// TODO fsd
+
+def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
+def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
+def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
+} // Predicates = [HasStdExtD]
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td?rev=320569&r1=320568&r2=320569&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td Wed Dec 13 03:37:19 2017
@@ -187,3 +187,36 @@ def FCVT_S_LU : FPUnaryOp_r_frm<0b110100
}
def : FPUnaryOpDynFrmAlias<FCVT_S_LU, "fcvt.s.lu", FPR32, GPR>;
} // Predicates = [HasStdExtF, IsRV64]
+
+//===----------------------------------------------------------------------===//
+// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtF] in {
+// TODO flw
+// TODO fsw
+
+def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
+def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
+def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
+
+// The following csr instructions actually alias instructions from the base ISA.
+// However, it only makes sense to support them when the F extension is enabled.
+// CSR Addresses: 0x003 == fcsr, 0x002 == frm, 0x001 == fflags
+// NOTE: "frcsr", "frrm", and "frflags" are more specialized version of "csrr".
+def : InstAlias<"frcsr $rd", (CSRRS GPR:$rd, 0x003, X0), 2>;
+def : InstAlias<"fscsr $rd, $rs", (CSRRW GPR:$rd, 0x003, GPR:$rs)>;
+def : InstAlias<"fscsr $rs", (CSRRW X0, 0x003, GPR:$rs), 2>;
+
+def : InstAlias<"frrm $rd", (CSRRS GPR:$rd, 0x002, X0), 2>;
+def : InstAlias<"fsrm $rd, $rs", (CSRRW GPR:$rd, 0x002, GPR:$rs)>;
+def : InstAlias<"fsrm $rs", (CSRRW X0, 0x002, GPR:$rs), 2>;
+def : InstAlias<"fsrmi $rd, $imm", (CSRRWI GPR:$rd, 0x002, uimm5:$imm)>;
+def : InstAlias<"fsrmi $imm", (CSRRWI X0, 0x002, uimm5:$imm), 2>;
+
+def : InstAlias<"frflags $rd", (CSRRS GPR:$rd, 0x001, X0), 2>;
+def : InstAlias<"fsflags $rd, $rs", (CSRRW GPR:$rd, 0x001, GPR:$rs)>;
+def : InstAlias<"fsflags $rs", (CSRRW X0, 0x001, GPR:$rs), 2>;
+def : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, 0x001, uimm5:$imm)>;
+def : InstAlias<"fsflagsi $imm", (CSRRWI X0, 0x001, uimm5:$imm), 2>;
+} // Predicates = [HasStdExtF]
Added: llvm/trunk/test/MC/RISCV/rvd-aliases-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rvd-aliases-valid.s?rev=320569&view=auto
==============================================================================
--- llvm/trunk/test/MC/RISCV/rvd-aliases-valid.s (added)
+++ llvm/trunk/test/MC/RISCV/rvd-aliases-valid.s Wed Dec 13 03:37:19 2017
@@ -0,0 +1,33 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+d -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+d -riscv-no-aliases=false \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+d -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+d -riscv-no-aliases=false \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+d < %s \
+# RUN: | llvm-objdump -d -mattr=+d -riscv-no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+d < %s \
+# RUN: | llvm-objdump -d -mattr=+d -riscv-no-aliases=false - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+d < %s \
+# RUN: | llvm-objdump -d -mattr=+d -riscv-no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+d < %s \
+# RUN: | llvm-objdump -d -mattr=+d -riscv-no-aliases=false - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+# TODO fld
+# TODO fsd
+
+# CHECK-INST: fsgnj.d ft0, ft1, ft1
+# CHECK-ALIAS: fmv.d ft0, ft1
+fmv.d f0, f1
+# CHECK-INST: fsgnjx.d ft1, ft2, ft2
+# CHECK-ALIAS: fabs.d ft1, ft2
+fabs.d f1, f2
+# CHECK-INST: fsgnjn.d ft2, ft3, ft3
+# CHECK-ALIAS: fneg.d ft2, ft3
+fneg.d f2, f3
Added: llvm/trunk/test/MC/RISCV/rvf-aliases-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rvf-aliases-valid.s?rev=320569&view=auto
==============================================================================
--- llvm/trunk/test/MC/RISCV/rvf-aliases-valid.s (added)
+++ llvm/trunk/test/MC/RISCV/rvf-aliases-valid.s Wed Dec 13 03:37:19 2017
@@ -0,0 +1,77 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+f -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+f -riscv-no-aliases=false \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+f -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+f -riscv-no-aliases=false \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
+# RUN: | llvm-objdump -d -mattr=+f -riscv-no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
+# RUN: | llvm-objdump -d -mattr=+f -riscv-no-aliases=false - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
+# RUN: | llvm-objdump -d -mattr=+f -riscv-no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
+# RUN: | llvm-objdump -d -mattr=+f -riscv-no-aliases=false - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+# TODO flw
+# TODO fsw
+
+# CHECK-INST: fsgnj.s ft0, ft1, ft1
+# CHECK-ALIAS: fmv.s ft0, ft1
+fmv.s f0, f1
+# CHECK-INST: fsgnjx.s ft1, ft2, ft2
+# CHECK-ALIAS: fabs.s ft1, ft2
+fabs.s f1, f2
+# CHECK-INST: fsgnjn.s ft2, ft3, ft3
+# CHECK-ALIAS: fneg.s ft2, ft3
+fneg.s f2, f3
+
+# The following instructions actually alias instructions from the base ISA.
+# However, it only makes sense to support them when the F extension is enabled.
+# CHECK-INST: csrrs t0, 3, zero
+# CHECK-ALIAS: frcsr t0
+frcsr x5
+# CHECK-INST: csrrw t1, 3, t2
+# CHECK-ALIAS: fscsr t1, t2
+fscsr x6, x7
+# CHECK-INST: csrrw zero, 3, t3
+# CHECK-ALIAS: fscsr t3
+fscsr x28
+
+# CHECK-INST: csrrs t4, 2, zero
+# CHECK-ALIAS: frrm t4
+frrm x29
+# CHECK-INST: csrrw t5, 2, t4
+# CHECK-ALIAS: fsrm t5, t4
+fsrm x30, x29
+# CHECK-INST: csrrw zero, 2, t6
+# CHECK-ALIAS: fsrm t6
+fsrm x31
+# CHECK-INST: csrrwi a0, 2, 31
+# CHECK-ALIAS: fsrmi a0, 31
+fsrmi x10, 0x1f
+# CHECK-INST: csrrwi zero, 2, 30
+# CHECK-ALIAS: fsrmi 30
+fsrmi 0x1e
+
+# CHECK-INST: csrrs a1, 1, zero
+# CHECK-ALIAS: frflags a1
+frflags x11
+# CHECK-INST: csrrw a2, 1, a1
+# CHECK-ALIAS: fsflags a2, a1
+fsflags x12, x11
+# CHECK-INST: csrrw zero, 1, a3
+# CHECK-ALIAS: fsflags a3
+fsflags x13
+# CHECK-INST: csrrwi a4, 1, 29
+# CHECK-ALIAS: fsflagsi a4, 29
+fsflagsi x14, 0x1d
+# CHECK-INST: csrrwi zero, 1, 28
+# CHECK-ALIAS: fsflagsi 28
+fsflagsi 0x1c
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