[PATCH] D41132: CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value

[Yaxun Liu via Phabricator via llvm-commits]

yaxunl added inline comments.


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Comment at: test/CodeGen/AMDGPU/debug-value.ll:1
+; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgizcl -mcpu=fi < %s
+target datalayout = "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"
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arsenm wrote:
> arsenm wrote:
> > Typo in cpu
> It's overridden by the attribute so it should just be dropped. Also could use -verify-machineinstrs, and should check for the DBG_VALUE
How do I check DBG_VALUE? It is not in the ISA assembly.


https://reviews.llvm.org/D41132