[PATCH] D41117: AMDGPU: Partially fix disassembly of MIMG instructions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: dp, SamWot, artem.tamazov.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, kzhuravl.

Stores failed to decode at all since they didn't have a
DecoderNamespace set. Loads worked, but did not change
the register width displayed to match the numbmer of
enabled channels.

      

The number of printed registers for vaddr is still wrong,
but I don't think that's encoded in the instruction so
there's not much we can do about that.

      

Image atomics are still broken. MIMG is the same
encoding for SI/VI, but the image atomic classes
are split up into encoding specific versions unlike
every other MIMG instruction. They have isAsmParserOnly
set on them for some reason. dmask is also special for
these, so we probably should not have it as an explicit
operand as it is now.


https://reviews.llvm.org/D41117

Files:
  lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
  lib/Target/AMDGPU/AMDGPUInstrInfo.h
  lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
  lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
  lib/Target/AMDGPU/MIMGInstructions.td
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
  test/MC/Disassembler/AMDGPU/mimg_vi.txt

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D41117.126561.patch
Type: text/x-patch
Size: 15095 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20171212/e656d62f/attachment.bin>