[PATCH] D40879: [X86][I86, I186, I286, I386, I486, Pentium]: Adding full coverage of MC encoding for the I86, I186, I286, I386, I486 and Pentium isa sets.<NFC>

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

You seem to have unwanted whitespace at the end of your CHECK lines (in both this patch and the previously committed patches).

I'd like to suggest an enhancement to this patch, the previously commited patches in this effort, and the other awaiting review: increase coverage by testing the "round-trip" of each instruction - i.e. check that instructions disassemble correctly as well by checking llvm-objdump output. You can see an example of this in the RISC-V backend (test/MC/RISCV/rv32i-valid.s for instance).

Extract below:

  # RUN: llvm-mc %s -triple=riscv32 -show-encoding \
  # RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
  # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
  # RUN:     | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
  
  # CHECK-INST: sb a0, 2047(a2)
  # CHECK: encoding: [0xa3,0x0f,0xa6,0x7e]
  sb a0, 2047(a2)
  # CHECK-INST: sh t3, -2048(t5)
  # CHECK: encoding: [0x23,0x10,0xcf,0x81]
  sh t3, -2048(t5)
  # CHECK-INST: sh t3, -2048(t5)
  # CHECK: encoding: [0x23,0x10,0xcf,0x81]
  sh t3, %lo(2048)(t5)
  # CHECK-INST: sw ra, 999(zero)
  # CHECK: encoding: [0xa3,0x23,0x10,0x3e]
  sw ra, 999(zero)


Repository:
  rL LLVM

https://reviews.llvm.org/D40879