[PATCH] D41096: [X86] Initial support for prefer-vector-width function attribute

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

> After this patch, I plan to start using this subtarget feature in X86ISelLowering.cpp to tell the type legalizer and assorted lowering code not to use 512-bit vectors.

I'm not sure this is a good idea.  As you mention, it gets complicated around user code which uses intrinsics, and it also gets complicated in cases where the ABI requires zmm registers.  And I'm not sure what benefit you're getting. Are you worried about DAGCombine introducing 512-bit vector operations?  The vectorizer using 512-bit vectors even though the target says not to?  Or some pre-isel pass other than the vectorizer randomly deciding to use 512-bit operations? Or something else I'm not thinking of?


https://reviews.llvm.org/D41096